Topic: Cairnsmore1 - Quad XC6SLX150 Board - page 105. (Read 286370 times)

Not sure it be as beneficial as you think.
Just because they are the designers/developers of the hardware and software does not guarantee it would be the fastest possible bitstream.
There could be other developers out there, given the chance whom could make a faster one. That is why Yohan has the developers program.

Now I doubt I'll be one of the developers to make the fastest bitstream, but I at least want to try and learn, so one day I could. Everyone has to start somewhere.

I think best option for customers and for enterpoint is to develop a bitstream that works only with boards manufactured by Enterpoint. That way Enterpoint gets a proper compensation for their work. They would also get new customers who want to use the faster bitstream.

There is no use selling that bitstream because potential buyers already have Enterpoint boards with that same bitstream.

Is this possible? I can not think any downsides?

Look forward to getting mine now even more.

OOooOOoOOooO. Do want.

Pretty please, a pic of them stacked with the correct connectors hooked up?

Enjoy

Even if shipping did not happen today, we had been warned also that this might happen

Pretty much satisfied, except the non bit-pay payment option.

Also: as eldentyrells tricone firmware is out and a "Board Developer Kit"  for the firmware http://www.tricone-mining.com/bdk.html, is enterpoint looking into that (you probably watched the development), or do you even think you can suceed in developing an even better formware without commission?

TY and Kudos so far,

Rampone

Thanks, that's a really helpful and very promising update.

Looking at roomservice's FPGA mining farm setup nicely shows how daisy chaining the communication will reduce the cable mess when setting up such a cluster of boards

Great job!

Update

Ok today was basically a good one and we think we have the in-built programmer sorted. We have a couple of tweeks to go in mainly related to us getting our unique sub-ID today for the USB from FTDI but it's basically working with the default ID. That tidy up should be done over the weekend. In parallel with this we are going to test the entire set of boards with this before we let them our of our clutches and send to those expecting them. Ok so that means they didn't ship today but we do want to be as sure as we can that there no bugs with a feature as important as this.

Our new bench and test kit was fitted into place today and we did a pile of testing today with boards. It will still take a few weeks to full refine the processes but it was working well today and doing everything we wanted out of this part of the process.

Bitstream - No progress today due to all the other things going on.

Packaging for the first 100 boards arrived late yesterday so we are ready to go on that front.

Stacking kit - We have not fully decided on what to offer as standard in the kit. Obvious will be pillars and an up/down cable. What we have not decided on are things like power linkages or r/a brackets for push pull fans.

UP/DOWN - Our structure and use of the UP/DOWN is now fairly well defined and a single USB cable should support an entire stack of boards with CGminer. MUltiple USB cable, multiple stack, combinations are also possible. There are a pile of commands we are putting in for extended CGminer facilities.

Some of you have asked about power linkages and input power. Using the PCIe power connector as input 1 board could be chained using the disk drive connector as those are simply hard wired together. I wouldn't recommend 2  but that might work. 2 units will take a greater current than the disk drive connector is technically rated for. The pheonix and jack are fed in through a diode to protect against bad polarity on the jack and bad wiring on the pheonix. That diode stops output power feeding on those 2.

For the ultimate of power routing the phenoix connector offers the ability to use heavy, low loss, wire gauges over 3 strands of 12V and 3 strands of GND so a heavy power distribution for a high current supply is possible and power bussing for a board stack is very practical. We talk a bit more of the options here as we get to the point of shipping large orders of Cairnsmore1.

Yohan

I have been thinking the same idea five per checking into the power supplies it seems you would be better going the other way one on the molex and four on pci-e six pin. The six pin provides I believe it is a dedicated 75w to the cable whereas the molex are shared on a cable that provides under the 75w per cable so there is chance you may overload those cables with a couple of boards on it.

Hi yohan,

while eagerly looking forward to get my Quads delivered, I started preparing the setup to prevent any additional delays after receipt - to be able to unpack the boards and start mining immediately 

Assuming each board will consume less than 40W, I prepared two 1.2kW PSUs and need some additional information to prepare power and communication cabling. If it was not already answered somewhere else, could you please respond to the following:

1) Stacking Kit
Does the stacking kit you are going to offer (or at least plan to) include cables to connect the up/down interfaces for daisy chaining? If so, does this include USB chaining and/or power supply?

2) Communication
Does the claimed 'Supports up and down interfaces for data flow within board stacking' imply that interconnected stacked boards need to be attached to only one USB port and will be detected as an array of tty interfaces (this is to know how many USB hubs I need to prepare)?

3) Power Supply
Are all the power connectors directly connected? What I would like to do is: stack 5 boards, connect the middle one via PCIe6 to PSU and connect all Molex connectors. Would this be doable to power all boards?


Thanks in advance (not to mention: kudos for keeping your promise)

One humble question to yohan: are the "spaceships" 1.1 on their way? or will shipping take until wednesday?

What about the "optional" stacking kit. How much does it cost extra?

And forgot to say: Awesome engineering speed so far. TY

My best guess for the bottleneck in compiling small designs into large FPGAs is in decrypting the floorplan files. Xilinx ISE has separate files for each chip in each package. All this information is a trade secret and serious effort was spent to encrypt and obfuscate it. So my guess for the best Xilinx FPGA design workstation would be the fastest server-grade CPU with a huge cache and lowest-latency RAM. Number of cores is immaterial as most of the workflow is single-threaded.

It was a good read, however since the article focused on how it's done on a spartan 3, I'm off to find one on the spartan 6 for see how things changed between the two.

Right, but I'm still not sure from that description where the bottleneck is - like I said, there are always ways to speed anything up, even if the speed difference isn't a lot. For instance, if the CPU doesn't actually relate to how long such a design placement takes, you could save money there and spend it somewhere else - for instance, on a 24-drive SSD array.

Picking a language was just a way of peaking interest amongst those more experienced than myself It worked.
Optimisation is something I'm known for in my software, so tweaking code to run a fraction of a ns faster per clock is something I will be petty enough to do to improve the bitstream.

1) Not a problem, I have that.
2) Noted.
3) Something to consider. I am patient, so if it takes a while to compile that doesn't bother me. Not like I don't have other projects. I will however see if I can find a uk seller doing something like that.

I'm sorry I probably wasn't clear enough.

The classic programming language compiler has the CPU architecture stored in the back end and it is always the same no matter whether you compile short or long program: in the end the RAM is linear.

The HDL programming language compiler also has to have the FPGA architecture stored in the back end. But unlike RAM the FPGA is not linear, it isn't even rectangular. Remember reading the complaints of eldentyrell and bitfury that the LX-150 has some things missing in the middle of the chip where it has the global clock buffer? Well the back-end of the design compiler (place and route) has to read in the detailed chip resource layout: SLICEs, BRAMs, DSPs (all those are explicitly documented) as well as undocumented switches and routing resources. Not only it has to read in all that data, in the place and route stage it has to explicitly fit the design into the floorplan. Even if the toolchain is all running from SSD disk it will still have to do those tasks. And those tasks aren't linear, the slowdown from LX9 to LX150 will not be 150/9, it will be noticeably more.

I find this interesting, because there is always a way to speed anything up, depending on where the bottleneck is. I've heard that it is strictly RAM dependent, so does this mean that with a low end processor and a low end hard drive, but 1TB of RAM it would be fast? If not, what combination of components relate to the speed loss? It seems to me that they way to speed it up would be to use a very fast processor, very fast RAM, and lots of RAM - more than 64GB to start with.

The language choice doesn't really matter. This project is so simple conceptually that the normal reasons for chosing the language are immaterial. This project stresses later stages of the design flow. Your experience with classical sequential programming languages is probably even counterproductive. What really helps is understanding the basics of logic design: combinatorial and sequential logic, flip-flops, etc. as well as any previous experience with declarative or parallel programming languages.

Most of the time you will spend researching various ways of transforming your program to convince the toolchain to accept your idea of how the design should be laid out. If you use Xilinx ISE as your toolchain then be aware of the following:

1) dense LX150 design will require more than 4GB of RAM during the later stages of the workflow, make sure that your machine has at least 8GB and the OS is 64-bit.
2) Xilinx changed the toolchain front-ends (both for Verilog & VHDL) with their "-6" FPGA families. When using tutorials prepared around older Xilinx FPGA families you may experience problems related to the corner-case differences in the HDL implementations.
3) even very small designs on a large chip take comparatively long time to compile. By the time the toolchain reads the floorplan and pinout of the LX150 chip the whole workflow on the LX9 chip will be done. Therefore for the beginners I recommend obtaining $98 Avnet Spartan-6 LX9 kit. If you start with a full LX150 design, especially the unrolled one, you will experience annoyingly long workflow iteration times, in the order of hour or two.

FPGA design is like playing tetris, chess and contract bridge all on the same board that is rectangular, not square.

ya but these things dont mine... YET.

This is what amazes me as well. Just look at the GLBSE: the scammiest "companies" get the most Bitcoins thrown at them.