Can anyone tell me what chip is used in BFL single?

eldentyrell

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Quote from: eldentyrell on April 29, 2012, 03:41:51 PM

I'll definitely pay up if/when he posts an IDCODE readout from the JTAG2 chain; right now all we know is that the board isn't hooked up properly (which might be due to BFL choosing a funky pinout).

The IDCODE readout has been found and the bounty has been paid:

https://bitcointalksearch.org/topic/m.886013

terrytibbs

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https://bitcointalksearch.org/topic/ok-i-confirmed-the-model-of-fpga-they-are-using-in-bfl-single-79825

abeaulieu

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Quote from: enmaku on May 02, 2012, 06:55:16 PM

Quote from: rjk on May 02, 2012, 02:50:02 PM

Quote from: enmaku on May 02, 2012, 02:16:42 PM

Quote from: mrb on March 20, 2012, 03:50:20 AM

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalksearch.org/topic/m.769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced Tongue

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

So it's looking less likely that we'll actually get time-to-failure data on the chips unless BFL does the testing themselves and released numbers.

Time-to-failure data on these chips would be quite difficult considering that bitcoin mining is typically an around-the-clock activity. I don't know how you would simulate this wear on the chips other than just running them and waiting until one fails, which hopefully won't be soon...

rjk

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1ngldh

Quote from: enmaku on May 02, 2012, 06:55:16 PM

Quote from: rjk on May 02, 2012, 02:50:02 PM

Quote from: enmaku on May 02, 2012, 02:16:42 PM

Quote from: mrb on March 20, 2012, 03:50:20 AM

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalksearch.org/topic/m.769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced Tongue

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

So it's looking less likely that we'll actually get time-to-failure data on the chips unless BFL does the testing themselves and released numbers.

As far as we know, the chips aren't even being binned, they just assemble them, see if they meet the specs, and ship. That's would be my assumption after hearing reports of some with units that throttle when others do not, in the same environment. Anyways, I have high hopes for the larger devices.

enmaku

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Quote from: rjk on May 02, 2012, 02:50:02 PM

Quote from: enmaku on May 02, 2012, 02:16:42 PM

Quote from: mrb on March 20, 2012, 03:50:20 AM

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalksearch.org/topic/m.769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced Tongue

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

So it's looking less likely that we'll actually get time-to-failure data on the chips unless BFL does the testing themselves and released numbers.

ionbasa

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Quote from: bombo999 on May 02, 2012, 01:58:33 PM

Quote from: ionbasa on May 02, 2012, 01:44:04 PM

http://www.atmel.com/products/Wireless/wifi/avr_xmega.aspx
hmm, how many pins are on the chips in the bfl single?

If you have your own single, just look yourself. If you don't have your own single, why do you care?

I don't have one which is why I was asking. The reason I care is because this thread is to help identify the chips used in the BFL Single, I like many others are curious and would want to know what chips are used.

rjk

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1ngldh

Quote from: enmaku on May 02, 2012, 02:16:42 PM

Quote from: mrb on March 20, 2012, 03:50:20 AM

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalksearch.org/topic/m.769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced Tongue

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

enmaku

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Quote from: mrb on March 20, 2012, 03:50:20 AM

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalksearch.org/topic/m.769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced Tongue

bombo999

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Quote from: ionbasa on May 02, 2012, 01:44:04 PM

http://www.atmel.com/products/Wireless/wifi/avr_xmega.aspx
hmm, how many pins are on the chips in the bfl single?

If you have your own single, just look yourself. If you don't have your own single, why do you care?

rjk

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1ngldh

Quote from: abeaulieu on May 02, 2012, 01:31:19 PM

Quote from: ||bit on May 02, 2012, 10:41:29 AM

Does anyone here understand what is delivered by Amtel with this service or product? An FPGA chip or a kind of hybrid?

http://www.atmel.com/products/Other/fpga_conversion_ulc/default.aspx

Interesting. Sounds like the product is more similar to an ASIC. Probably VERY costly though since the design/conversion is handled entirely by Atmel.

It's the same thing as Xilinx Easy-Path, Altera Hardcopy, etc. Also known as sASIC.

ionbasa

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http://www.atmel.com/products/Wireless/wifi/avr_xmega.aspx
hmm, how many pins are on the chips in the bfl single?

abeaulieu

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Quote from: ||bit on May 02, 2012, 10:41:29 AM

Does anyone here understand what is delivered by Amtel with this service or product? An FPGA chip or a kind of hybrid?

http://www.atmel.com/products/Other/fpga_conversion_ulc/default.aspx

Interesting. Sounds like the product is more similar to an ASIC. Probably VERY costly though since the design/conversion is handled entirely by Atmel.

||bit

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Does anyone here understand what is delivered by Amtel with this service or product? An FPGA chip or a kind of hybrid?

http://www.atmel.com/products/Other/fpga_conversion_ulc/default.aspx

seriouscoin

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Quote from: bulanula on April 30, 2012, 02:39:14 AM

Come on, we all know ATMEL is not the FPGA chip that does the hashings but just a side ASIC used for USB or something ...

Just Shut the fck up and get out of this forum. Loser

bulanula

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Come on, we all know ATMEL is not the FPGA chip that does the hashings but just a side ASIC used for USB or something ...

eldentyrell

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Quote from: antirack on April 26, 2012, 11:00:44 PM

After a little bit of reading, I found that protecting the JTAG port of an Altera FPGA seems to be a standard feature.

Quote from: antirack on April 27, 2012, 08:15:41 AM

In Cyclone III LS FPGAs, the native state of JTAG is restricted to only those
instructions required for compliance to the IEEE specification.

IDCODE is "required for compliance to the IEEE specification" so this won't affect it.

Quote from: antirack on April 26, 2012, 11:00:44 PM

Warning: TDO seems to be stuck at 1

Try setting the TCK frequency to something absurdly low ("frequency 1000" in urjtag).

If nothing changes, then you're probably right that:

Quote from: abeaulieu on April 27, 2012, 05:54:04 AM

they may have just switched the pins around on JTAG2. Who knows. If it would be me trying to protect my design, I'd do that too.

You'll have to try different pin hookups, but it's not as bad as it sounds. The first step is to find out which (if any) of the 10 pins has a driver on it; that's TDO. Then, for each of the remaining nine pins try wiggling them one at a time to figure out which one is TCK. Then all you need is TMS. You can get the IDCODE readout without TDI.

Quote from: rjk on April 27, 2012, 03:50:51 PM

Don't forget to email eldentyrell and ask for your 5 BTC. Cheesy

I'll definitely pay up if/when he posts an IDCODE readout from the JTAG2 chain; right now all we know is that the board isn't hooked up properly (which might be due to BFL choosing a funky pinout).

antirack

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Immersionist

Pins not trimmed, orientation correct. And I'll leave the logic analyzer part to the pros such as yourself.

ElectricMucus

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Well then did you check if too short pins were an issue in your case? Did you check the right orientation? Did you use a logic analyzer to get more information?
But if you are capable (which we assume) that shouldn't even be part of the discussion. So you are right we should move on.

Still you didn't answer my question: Are your pins trimmed?

antirack

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Come on. Of course I have a single otherwise how could I connect a JTAG cable? JTAG1 and JTAG2 is written right next to them. And if it wouldn't be a JTAG header I guess the Atmel MCU wouldn't be talking to it. And no, my pins are not trimmed, on any of my 10 units (you can directly look at the JTAG headers through the "grill")

If you have nothing to add to this thread, could you please move on?

ElectricMucus

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Quote from: mem on April 28, 2012, 10:36:28 PM

Quote from: ElectricMucus on April 28, 2012, 02:44:01 PM

That or the whole thing is made up on the spot, upto the point of someone actually receiving a BFL single. (Yeah I am siding with mem here.)

Better put your flame suite on mate, questioning the almighty BFL will get you burned as a witch in these parts Wink

Can handle it I was labeled as a troll numerous times, someone even bothered to put me on a "list" as a public pillory of people to avoid.
Pretty hilarious.

Quote from: antirack on April 29, 2012, 06:29:08 AM

And back on topic.

I noticed something strange with the JTAG header in this photo from BFL (original here):
http://image.bayimg.com/oaoolaade.jpg

Look at the left JTAG header (JTAG2). Is it just me or did they trim some of the pins?

Do you have a BFL or not? Are your pins trimmed?
That wouldn't stop anyone equipped with a soldering iron (about anybody who would even know what jtag is)

Which brings me to the next issue: How do you know it's a jtag port in the first place?

Topic: Can anyone tell me what chip is used in BFL single? (Read 12750 times)