They produced a working Mars FPGA based on their ASIC design at least. That proves at least chip-designing chops and the ability to code it to a working state.
Actually, you would normally develop an ASIC based on a FPGA design and not vice versa: http://en.wikipedia.org/wiki/FPGA_prototype
RTLs like VHDL/Verilog need to be specifically translated into ASIC designs, FPGAs are programmable after all - when using an FPGA there's simply no such thing as dealing with things at the wafer-level.
FPGAs are comparatively easy to use, even by hobbyists with some background experience (CS/EE), with very little resources being required. These days you are exposed to FPGA and VHDL in college.
Real ASICs designs are a hugely different thing however.
Saying that an ASIC company "has FPGA experience" is as informative as saying that Albert Einstein knew arithmetics. There's simply NO way for an ASIC company not to know about FPGAs.
You would expect an airline pilot to be able to land a single-engine airplane, but you would not necessarily expect a single-engine pilot to land an A380, roger ?
). 
I saw the potential in KnC as soon as they confirmed ORSoC.
