Topic: Custom FPGA Board for Sale! - page 15. (Read 91608 times)

Very cool. Looks promising! Unfortunately the investment price is too high to make much sense.

It's just helps to justify it more, there's no easy way to cool these things well with such a small footprint, I haven't seen a heatsink that's alot higher then it's length/width (at least not where I live), I can't cool these passively, so adding a small fan ontop was the easiest way without having to scrounge for specialty heatsinks (the current heatsinks I use are about USD$1 each, affordable, the fan adds a few more bucks.)

Without a fan you'd be running into finger scorching temps. I have no idea what the actual on die temps are like (the chip is encased in a plastic epoxy package), but I'd definitely not be running 24/7 at those temps.

I know at this point the board may seem to be pricey, but the costs for the board and components for low volume orders are high, let me put it into context. The spartan-6 based dev board that FPGAminer uses during dev costs USD$1000, this is less then 1/2 that cost, yes it doesn't have all the other features, but that's what we want for a mining board.

We'd like to at this point sell off a couple of the boards I have on hand and recoup some of the original investment to continue spinning the next batch of boards.

Support for the original board (this batch) will continue for as long as feasible, upgrades may come in little modules that you can plug into the Jtag port (for chaining etc.), we aren't planning to screw the early adopters over.

Here's something else I just realized. Li wrote this in another thread earlier today:


So if the chip gets hot, it starts using more power. Looks like the ~0.5W of the fan is justified...

It is because the FG484 chip is about 28mmx28mm, plastic packaging. Only a 28X28mm heatsink can add to the chip. So a small fan is needed.

That's a smart question...

You would be surprised how much heat 6W can generate. I talked about this a long time ago with fpgaminer. He said something like, "It's not so surprising that you need to put a fan on an FPGA. The surprising thing is that a 6990 doesn't burn your house down."       Maybe the difference is, a 6990 already gets some airflow, being inside the computer case.

But yeah, we might be able to get away with no fan. I think the chip doesn't start incinerating 'til over 100C. fpgaminer was working on an error-detecting code. If the chip gets too hot and starts making mistakes, it will detect the mistakes and stop.

You bitcoin crowd sure are a tough sell. I think I will try to sell these on eBay

P.S. The board has been running non-stop for about 18 hours now    

6.8W isn't a lot compared to a GPU but it is a TON compared to these FPGAs that normally run at 3 watts or below. FPGAs are really being pushed in these applications.

I presume you have done the obvious optimisations that clearly mean less calculations per double hash:
pre-calculating the first 3 rounds and not bothering to calculate the last 3.5 rounds since you don't need them at all ...

I was just wondering ... why does a 6.8W FPGA need a fan?

A cheap 40mm fan is like 0.07Amps so about 0.8Watts - an increase is power of about 12% - 12% is a lot.

My 6950's I set to not run the fan when they are under 60degress.
At 350Mh/s they stay over 60degress, but a drop to something like 250-300Mh/s and they will stay under the 60degrees and not even need the fans on.
... and we are talking over 100Watts (350Mh/s is about 180Watts)

Just wondering about the decision to bother to put a fan on it all ...

Not really. Those are GPU optimizations, and are focused on reducing the total number of calculations needed to compute the final hash. That benefits the GPU's performance, but none of them would really have a useful impact on an FPGA's MH/s performance. So I haven't implemented most of them, because they aren't too helpful, would clutter the code, and my time is better spent elsewhere for now.

This thread gives a good run down of all the optimizations being implemented on GPUs.
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thanks! i did see this before and had lost track of it. appreciate the link.  so basically similar algo optimizations were implemented on your fpga code?

I'm mostly just the firmware designer, but I will try to chime in on a few things here for everyone's benefit

First and foremost, I do not think it has been made clear that these boards are firmware upgradeable. As improvements are made to the Open Source FPGA Bitcoin Mining project, new firmware will be generated and made available. Just like we see improvements to GPU software and you can drive more out of your dusty 5850s

Personally, I am very excited about this little board as a development platform Beats the heck out of my $1000 dev kit 


Connecting Multiple Boards
As newMeat1 has hinted at, this was being fleshed out and worked on even before these first boards were sent into production. I'll be playing around with FTDI chips and/or micros, and see if we can get a nice, simple solution that will be backwards compatible with existing boards, streamline future designs, and scale well for multiple boards.

I have an ~8 year old laptop that could probably drive these things All current GPU mining rigs can also drive it, in addition to driving their GPUs.

The Spartan-2 series is likely too old to push many MH, if any. That particular chip only has ~1K CLBs, for example.

Think of an FPGA as a massive breadboard, with LUTs glued onto it in columns and rows. The breadboards are your "routing fabric" and allow you to choose how you connect the LUTs, and of course you can load the LUTs with whatever configuration you want. That's your most basic FPGA architecture. Just note that there is a "routing cost" proportional to the distance you try to route. For example, connecting one LUT to another half way across your massive breadboard would lead to a massive signal delay.

This thread gives a good run down of all the optimizations being implemented on GPUs.

On optimization of mining algo (be it on GPUs, CPUs or FPGAs) is there a post that describes all available optimizations?  I'd like to learn about it.  Can someone point me to it please?  or is the computing H+K+W[0] in the previous round pretty much the only optimization so far?

LUTs are sometimes involved in certain specialised kinds of routing, but most of the routing is done through a dedicated routing fabric in which the LUTs are embedded. As I understand it this is one of the things that distinguishes FPGAs from other forms of programmable logic like CPLDs.

Yeah, FPGAs very power-efficient but the upfront cost is nasty for every solution I've seen so far. On the plus side, as newMeat1 says you can keep going well after GPU miners have to give up...

Edit:
That reminds me, an interesting factoid: unless he's been deliberately misleading people, at the time he had the ASICs made he didn't actually know about the optimisation of computing H+K+W[0] in the previous round, which improves performance for free by reducing the critical path (at least on FPGAs).

I've read the irc log and just discovered that there is a wiki entry. But are those claims reasonable?
Besides the rumors, I don't think that a asic would be that desirable even by someone with alot of budget. The feature size is much too large for these low production units and really cornering the market wouldn't be possible considering that the latest fpgas, even with all its disadvantages have the smallest feature size of any product now.
If this trend continues it might even surpass the efficiency of a low production asic or any asic for that matter if they become the dominant technology.

But the strongest reason imo is that you can't update asics, so I think he can suck it  

That's OK. People like artForz get it. What happens when only half as many bitcoins are created with every block? Or farther down the road, when miners are supported mostly by transaction fees?

What I'm getting at is-- the farther along we go, the more important computational efficiency becomes. At some point GPU's aren't gonna cut it.

*Sorry to be curt in my original reply

I would so buy one or two but $440 is a bit too much to invest in 100 Mhash. It would take a seriously long time to earn back that original investment. I just picked up a 5870 for $180 and that nets me 393 Mhash/s , so 3x the amount this board does at a more reasonable cost.

According to my calculations it would take  23.66 months to pay for this board - assuming btc prices stay at ~10.98.

Are you certain? Aren't the LUTs involved in routing too? I always thought that they were either configured as logic or routing node.

I have to admit my understandings of the workings of fpgas isn't quite as good.

Errrm... none, because the rotations are just rearranging bits in a fixed way. They do use up routing resources though. (I'm not involved with the design and sale of this board but I did contribute a few performance-related improvements to the FPGA code.)

Consider me in. I think the perfect FPGA miner is something in between this design and the sophisticated one we've been developing in the "modular" thread. Let's work together and get things moving, at a reasonable cost and in reasonable time.

wait what else can fpga board do??
i dont have much expirence with them.

diid u get your chips from http://avnetexpress.avnet.com?