Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED - page 33.

niko2004x

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Activity: 126

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Quote from: nerdralph on April 10, 2017, 07:49:03 AM

Quote from: niko2004x on April 09, 2017, 09:32:59 PM

Quote from: nerdralph on April 09, 2017, 07:37:38 PM

I took a break from figuring out memory controller registers and added R9 strap format to ohgodadecode through a compile-time flag.
CFLAGS=-DSTRAP_R9=1 make
https://github.com/nerdralph/OhGodADecode

Here it is decoding a strap (1500Mhz) from my custom Tonga BIOS. Next I'll probably do a new version of the Tonga bios with tuned straps.

Code:

./ohgodadecode 7771332000000000EF516A3790550F1232179A05006AE40022AA1C0874021420CA89C0A8020000C01510232859283315
TRCDW=15 TRCDWA=15 TRCDR=20 TRCDRA=20 TRRD=6 TRC=55 Pad0=0

TNOPW=0 TNOPR=0 TR2W=25 TCCDL=2 TR2R=5 TW2R=15 Pad0=0 TCL=18 Pad1=0

TRP_WRA=50 TRP_RDA=23 TRP=104 TRFC=44 Pad0=0

PA2RDATA=2 Pad0=1 PA2WDATA=6 Pad1=0 TFAW=4 TCRCRL=7 TCRCWL=0 TFAW32=0

MC_SEQ_MISC1: 0xCA201402
MC_SEQ_MISC3: 0x02A8C089
MC_SEQ_MISC8: 0x15C00000

ACTRD=16 ACTWR=35 RASMACTRD=40 RASMACTWR=89

RAS2RAS=40 RP=51 WRPLUSRP=21 BUS_TURN=0

p.s. just noticed there might be a bug in MC_SEQ_MISC_TIMING2 decoding, since Pad0=1. May have to dig through the amdgpu register initialization code to make sure I have the right offset in the strap for it.

Which card has this timing string for 1500 strap?
I only saw this timing string for 1375 strap in Elpida EDW4032BABG in R9 290X/380/390/390X.

Good catch. It's the 1500 strap in my custom Tonga BIOS, which I originally copied from the 1375 strap. I'll double-check my mods to the decode tool with your atom_rom_timings code to see if I can find the bug(s).

Well my knowledge is (at least partially) from statistical analysis, so 'all atombios timing tables in existence' database is a nice by-product.

nerdralph

sr. member

Activity: 588

Merit: 251

Found the bug. I had made a mistake in _SEQ_MISC_TIMING_FORMAT_R9 so that it was 33 bits long instead of 32, which skewed the offsets for everything after it.
Here's the output from the fixed version:

Code:

./ohgodadecode 7771332000000000EF516A3790550F1232179A05006AE40022AA1C0874021420CA89C0A8020000C01510232859283315
TRCDW=15 TRCDWA=15 TRCDR=20 TRCDRA=20 TRRD=6 TRC=55 Pad0=0

TNOPW=0 TNOPR=0 TR2W=25 TCCDL=2 TR2R=5 TW2R=15 Pad0=0 TCL=18 Pad1=0

TRP_WRA=50 TRP_RDA=23 TRP=20 TRFC=89 Pad0=0

PA2RDATA=0 Pad0=0 PA2WDATA=0 Pad1=0 TFAW=10 TCRCRL=3 TCRCWL=4 TFAW32=7

MC_SEQ_MISC1: 0x20140274
MC_SEQ_MISC3: 0xA8C089CA
MC_SEQ_MISC8: 0xC0000002

ACTRD=21 ACTWR=16 RASMACTRD=35 RASMACTWR=40

RAS2RAS=89 RP=40 WRPLUSRP=51 BUS_TURN=21

nerdralph

sr. member

Activity: 588

Merit: 251

Quote from: niko2004x on April 09, 2017, 09:32:59 PM

Quote from: nerdralph on April 09, 2017, 07:37:38 PM

I took a break from figuring out memory controller registers and added R9 strap format to ohgodadecode through a compile-time flag.
CFLAGS=-DSTRAP_R9=1 make
https://github.com/nerdralph/OhGodADecode

Here it is decoding a strap (1500Mhz) from my custom Tonga BIOS. Next I'll probably do a new version of the Tonga bios with tuned straps.

Code:

./ohgodadecode 7771332000000000EF516A3790550F1232179A05006AE40022AA1C0874021420CA89C0A8020000C01510232859283315
TRCDW=15 TRCDWA=15 TRCDR=20 TRCDRA=20 TRRD=6 TRC=55 Pad0=0

TNOPW=0 TNOPR=0 TR2W=25 TCCDL=2 TR2R=5 TW2R=15 Pad0=0 TCL=18 Pad1=0

TRP_WRA=50 TRP_RDA=23 TRP=104 TRFC=44 Pad0=0

PA2RDATA=2 Pad0=1 PA2WDATA=6 Pad1=0 TFAW=4 TCRCRL=7 TCRCWL=0 TFAW32=0

MC_SEQ_MISC1: 0xCA201402
MC_SEQ_MISC3: 0x02A8C089
MC_SEQ_MISC8: 0x15C00000

ACTRD=16 ACTWR=35 RASMACTRD=40 RASMACTWR=89

RAS2RAS=40 RP=51 WRPLUSRP=21 BUS_TURN=0

p.s. just noticed there might be a bug in MC_SEQ_MISC_TIMING2 decoding, since Pad0=1. May have to dig through the amdgpu register initialization code to make sure I have the right offset in the strap for it.

Which card has this timing string for 1500 strap?
I only saw this timing string for 1375 strap in Elpida EDW4032BABG in R9 290X/380/390/390X.

Good catch. It's the 1500 strap in my custom Tonga BIOS, which I originally copied from the 1375 strap. I'll double-check my mods to the decode tool with your atom_rom_timings code to see if I can find the bug(s).

laik2

sr. member

Activity: 652

Merit: 266

I think that's the correct format output:

Quote

--> HEX strap: 7771332000000000EF516A3790550F1232179A05006AE40022AA1C0874021420CA89C0A8020000C 01510232859283315

--> MC_SEQ_WR_CTL_D0
DAT_DLY = 7, DQS_DLY = 7, DQS_XTR = 1, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 7, OEN_EXT = 3

--> MC_SEQ_WR_CTL_D1
DAT_DLY = 0, DQS_DLY = 0, DQS_XTR = 0, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 0, OEN_EXT = 0

--> MC_SEQ_RAS_TIMING
TRCDW = 15, TRCDWA = 15, TRCDR = 20, TRCDRA = 20, TRRD = 6, TRC = 55, Pad0 = 0

--> MC_SEQ_CAS_TIMING
TNOPW = 0, TNOPR = 0, TR2W = 25, TCCLD = 2, TR2R = 5, Pad0 = 0, TW2R = 15, TCL = 18, Pad1 = 0

--> MC_SEQ_MISC_TIMING
TRP_WRA = 50, Pad0 = 0, TRP_RDA = 23, Pad1 = 0, TRP = 20, TRFC = 89, Pad2 = 0

--> MC_SEQ_MISC_TIMING2
PA2RDATA = 0, Pad0 = 0, PA2WDATA = 0, Pad1 = 0, FAW = 10, TREDC = 3, TWEDC = 4, T32AW = 7, Pad2 = 0, TWDATATR = 0

--> MC_SEQ_PMG_TIMING
TCKSRE = 2, Pad0 = 0, TCKSRX = 2, Pad1 = 0, TCKE_PULSE = 10, TCKE = 10, SEQ_IDLE = 7, Pad2 = 0, TCKE_PULSE_MSB = 0, SEQ_IDLE_SS = 8

--> MC_ARB_DRAM_TIMING
ACTRD = 21, ACTWR = 16, RASMACTRD = 35, RASMACTWR = 40

--> MC_ARB_DRAM_TIMING2
RAS2RAS = 89, RP = 40, WRPLUSRP = 51, BUS_TURN = 21

niko2004x

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Activity: 126

Merit: 10

Quote from: nerdralph on April 09, 2017, 07:37:38 PM

I took a break from figuring out memory controller registers and added R9 strap format to ohgodadecode through a compile-time flag.
CFLAGS=-DSTRAP_R9=1 make
https://github.com/nerdralph/OhGodADecode

Here it is decoding a strap (1500Mhz) from my custom Tonga BIOS. Next I'll probably do a new version of the Tonga bios with tuned straps.

Code:

./ohgodadecode 7771332000000000EF516A3790550F1232179A05006AE40022AA1C0874021420CA89C0A8020000C01510232859283315
TRCDW=15 TRCDWA=15 TRCDR=20 TRCDRA=20 TRRD=6 TRC=55 Pad0=0

TNOPW=0 TNOPR=0 TR2W=25 TCCDL=2 TR2R=5 TW2R=15 Pad0=0 TCL=18 Pad1=0

TRP_WRA=50 TRP_RDA=23 TRP=104 TRFC=44 Pad0=0

PA2RDATA=2 Pad0=1 PA2WDATA=6 Pad1=0 TFAW=4 TCRCRL=7 TCRCWL=0 TFAW32=0

MC_SEQ_MISC1: 0xCA201402
MC_SEQ_MISC3: 0x02A8C089
MC_SEQ_MISC8: 0x15C00000

ACTRD=16 ACTWR=35 RASMACTRD=40 RASMACTWR=89

RAS2RAS=40 RP=51 WRPLUSRP=21 BUS_TURN=0

p.s. just noticed there might be a bug in MC_SEQ_MISC_TIMING2 decoding, since Pad0=1. May have to dig through the amdgpu register initialization code to make sure I have the right offset in the strap for it.

Which card has this timing string for 1500 strap?
I only saw this timing string for 1375 strap in Elpida EDW4032BABG in R9 290X/380/390/390X.
Decoding for MC_SEQ_MISC_TIMING looks wrong (at least not consistent with decoding of timing string for the same strap and memory type in RX).
MC_SEQ_MISC_TIMING2 looks wrong too, the way a see it (my tool does not work with timing strings only tables and bioses, so some hacks):

Code:

$ python atom_timings_editor.py --type R9 -r -I db/R9/Elpida/EDW4032BABG/01.straps -O - |grep 137500 | sed -r "s/[ ,]\[/\n\n[/g"
137500 0 7771332000000000ef516a3790550f1232179a05006ae40022aa1c0874021420ca89c0a8020000c01510232859283315

[TRCDW=015,TRCDWA=015,TRCDR=020,TRCDRA=020,TRRD=006,TRC=055,unused1=000]

[TNOPW=000,TNOPR=000,TR2W=025,TCCDL=002,TR2R=005,TW2R=015,unused1=000,TCL=018,unused2=000]

[TRP_WRA=050,unused1=000,TRP_RDA=023,unused2=000,TRP=020,TRFC=089,unused3=000]

[PA2RDATA=000,unused1=000,PA2WDATA=000,unused2=000,FAW=010,TREDC=003,TWEDC=004,T32AW=007,unused3=000,TWDATATR=000]

[TCKSRE=002,unused1=000,TCKSRX=002,unused2=000,TCKE_PULSE=010,TCKE=010,SEQ_IDLE=007,unused3=000,TCKE_PULSE_MSB=000,SEQ_IDLE_SS=008]

[ACTRD=021,ACTWR=016,RASMACTRD=035,RASMACTWR=040]

[RAS2RAS=089,RP=040,WRPLUSRP=051,BUS_TURN=021]

$ python atom_timings_editor.py --type RX -r -I db/RX/Elpida/EDW4032BABG/01.straps -O - |grep 137500 | sed -r "s/[ ,]\[/\n[/g"
137500 0 777000000000000022aa1c00ef516a3790550f14b20b9505006ae40074021420ca89c0a8020004c01510232859283315

[TRCDW=015,TRCDWA=015,TRCDR=020,TRCDRA=020,TRRD=006,TRC=055,unused1=000]

[TNOPW=000,TNOPR=000,TR2W=025,TCCDL=002,TR2R=005,TW2R=015,unused1=000,TCL=020,unused2=000]

[TRP_WRA=050,TRP_RDA=023,unused1=000,TRP=020,unused2=000,TRFC=089,unused3=000]

[PA2RDATA=000,unused1=000,PA2WDATA=000,unused2=000,FAW=010,TREDC=003,TWEDC=004,T32AW=007,unused3=000,TWDATATR=000]

[TCKSRE=002,unused1=000,TCKSRX=002,unused2=000,TCKE_PULSE=010,TCKE=010,SEQ_IDLE=007,unused3=000,TCKE_PULSE_MSB=000,SEQ_IDLE_SS=000]

[ACTRD=021,ACTWR=016,RASMACTRD=035,RASMACTWR=040]

[RAS2RAS=089,RP=040,WRPLUSRP=051,BUS_TURN=021]

EDIT: MC_ARB_DRAM_TIMING2, MC_ARB_DRAM_TIMING looks misaligned too.
Or at least i think 59283315 should be decoded as 89, 40, 51, 21.

nerdralph

sr. member

Activity: 588

Merit: 251

I took a break from figuring out memory controller registers and added R9 strap format to ohgodadecode through a compile-time flag.
CFLAGS=-DSTRAP_R9=1 make
https://github.com/nerdralph/OhGodADecode

Here it is decoding a strap (1500Mhz) from my custom Tonga BIOS. Next I'll probably do a new version of the Tonga bios with tuned straps.

Code:

./ohgodadecode 7771332000000000EF516A3790550F1232179A05006AE40022AA1C0874021420CA89C0A8020000C01510232859283315
TRCDW=15 TRCDWA=15 TRCDR=20 TRCDRA=20 TRRD=6 TRC=55 Pad0=0

TNOPW=0 TNOPR=0 TR2W=25 TCCDL=2 TR2R=5 TW2R=15 Pad0=0 TCL=18 Pad1=0

TRP_WRA=50 TRP_RDA=23 TRP=104 TRFC=44 Pad0=0

PA2RDATA=2 Pad0=1 PA2WDATA=6 Pad1=0 TFAW=4 TCRCRL=7 TCRCWL=0 TFAW32=0

MC_SEQ_MISC1: 0xCA201402
MC_SEQ_MISC3: 0x02A8C089
MC_SEQ_MISC8: 0x15C00000

ACTRD=16 ACTWR=35 RASMACTRD=40 RASMACTWR=89

RAS2RAS=40 RP=51 WRPLUSRP=21 BUS_TURN=0

p.s. just noticed there might be a bug in MC_SEQ_MISC_TIMING2 decoding, since Pad0=1. May have to dig through the amdgpu register initialization code to make sure I have the right offset in the strap for it.

nerdralph

sr. member

Activity: 588

Merit: 251

Quote from: padrino on April 09, 2017, 08:30:23 AM

AMD's UMR tool makes setting many registers a lot easier than it used to be, it's good to keep around for changing register values...

It's almost information overload though... And I still find organizing the CUs into engines and shader groups confusing. I'd just number them from 0..

Code:

~/git/umr/build/src/app$ sudo ./umr -wa | head -25
SE SH CU SIMD WAVE# WAVE_STATUS PC_HI PC_LO INST_DW0 INST_DW1 EXEC_HI EXEC_LO HW_ID GPRALLOC LDSALLOC TRAPSTS IBSTS TBA_HI TBA_LO TMA_HI TMA_LO IB_DBG0 M0
0 0 1 0 0 00010c01 00000001 046737e0 bf8c0070 00024b1f ffffffff ffffffff 40620100 01001700 0000c098 20000000 00006000 00000000 00000000 00000000 00000000 00000b06 00010000
>SGPRS[0..3] = { ffffffff, 00000040, 77777777, 77777777 }
>SGPRS[4..7] = { 040fbf00, 00000001, 00f3fffd, 00000010 }
>SGPRS[8..11] = { 083b0000, 00000001, ffffffff, ffffffff }
>SGPRS[12..15] = { bbbbbbbb, bbbbbbbb, 44444444, 44444444 }
>SGPRS[16..19] = { 44444444, 44444444, 2698ede5, 4044d6c3 }
>SGPRS[20..23] = { 0000000f, d77e3ff3, 9e8676f6, fc0d519a }
>SGPRS[24..27] = { 04543881, 7b52b071, d6470a37, 8cc0ba31 }
>SGPRS[28..31] = { 0a3dbeae, 7db6ab47, 00000000, 00000000 }
>pgm[6@1046737d0] = d285001e
>pgm[6@1046737d4] = 00024b1e
>pgm[6@1046737d8] = d285000b
>pgm[6@1046737dc] = 00024b0b
>pgm[6@1046737e0] = bf8c0070
>pgm[6@1046737e4] = 2a3e5f1f
>pgm[6@1046737e8] = 2a365d1b
>pgm[6@1046737ec] = 2a485b24

p.s. I'm finding it seems to have copied the out-of-date register bitfields used in the kernel. For example mmMC_ARB_RFSH_RATE supposedly only uses the lower 8 bits for powermode0, but I'm seeing values in the upper 16 bits too.

padrino

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Activity: 1428

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https://www.bitworks.io

AMD's UMR tool makes setting many registers a lot easier than it used to be, it's good to keep around for changing register values...

nerdralph

sr. member

Activity: 588

Merit: 251

Quote from: Wolf0 on April 08, 2017, 07:25:14 PM

Quote from: nerdralph on April 08, 2017, 07:23:06 PM

Anyone find out how to change the refresh interval through the straps or elsewhere in the BIOS? I'm not talking about tRFC the refresh command delay, I'm talking about the refresh interval or period (tREFI & tREF). I want to reduce the refresh overhead by refreshing the RAM less frequently. Wolf says he's only been able to do it by directly writing to the memory controller registers. Obviously changing values in the strap or the BIOS would be easier. Unless Wolf decides to release that code too... :-)

I'd give it to you, but you'd release it Tongue

In this case I'm not sure if I'll release it. It's looking like it won't take a lot of experimenting to figure out though.
https://github.com/torvalds/linux/blob/5924bbecd0267d87c24110cbe2041b5075173a25/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h#L73

laik2

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Activity: 652

Merit: 266

Quote from: doktor83 on April 09, 2017, 01:32:30 AM

Quote from: OhGodAGirl on March 21, 2017, 04:18:15 AM

I'll prepare documentation this weekend to go along with all of this, that makes it clear what you're doing when you change stuff; and what each value is used for. You're very welcome. This stuff shouldn't be kept hidden - the straps are the important things, and people will still pay handsomely for straps.

Did this happen ? Cheesy

It was more of a "bla bla" Cheesy

doktor83

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Activity: 2548

Merit: 626

Quote from: OhGodAGirl on March 21, 2017, 04:18:15 AM

I'll prepare documentation this weekend to go along with all of this, that makes it clear what you're doing when you change stuff; and what each value is used for. You're very welcome. This stuff shouldn't be kept hidden - the straps are the important things, and people will still pay handsomely for straps.

Did this happen ? Cheesy

nerdralph

sr. member

Activity: 588

Merit: 251

Anyone find out how to change the refresh interval through the straps or elsewhere in the BIOS? I'm not talking about tRFC the refresh command delay, I'm talking about the refresh interval or period (tREFI & tREF). I want to reduce the refresh overhead by refreshing the RAM less frequently. Wolf says he's only been able to do it by directly writing to the memory controller registers. Obviously changing values in the strap or the BIOS would be easier. Unless Wolf decides to release that code too... :-)

laik2

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Activity: 652

Merit: 266

Quote from: Oakey22 on April 07, 2017, 03:35:35 PM

I have just got a few ASUS Dual rx480's and they have no settings for the i2c in whattool, it still possible to add this to the ROM using hex? as I understand its the 8D 00 ** 00 part that needs adding.

Samsung memory too

Anyone know or can give me a guiding hand?

It doesn't have default VDDC offset, hense it "might" support VDDC/VDDCI offsets both...I will confirm in about 15 days when my 4g dual strix arrive.

Oakey22

sr. member

Activity: 489

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I have just got a few ASUS Dual rx480's and they have no settings for the i2c in whattool, it still possible to add this to the ROM using hex? as I understand its the 8D 00 ** 00 part that needs adding.

Samsung memory too

Anyone know or can give me a guiding hand?

Zorg33

jr. member

Activity: 144

Merit: 2

Any success with micron?
I tested an msi 470 8GB Micron yesterday and most I could get was 27.3mh/s with the 1750 strap. Above 1950 it was not stable.
I heard of 30mh. Is it possible?

niko2004x

member

Activity: 126

Merit: 10

Quote from: zeftcool on April 06, 2017, 01:33:10 AM

Quote from: laik2 on April 06, 2017, 01:03:57 AM

Quote from: zeftcool on April 06, 2017, 12:53:32 AM

00 8D ** 00 VDDC control
work for nitro+ card but not work for nitro card

It works for all which bios can be opened with atombiosreader. I had only one XFX that didn't have(or couldn't find it) VOI.

yes it work but just for IR3567B nitro+ card
nitro card using NCP81022 and it not work
they are different card
all nitro and nitro+ bios is same and can be oppened by atombiosreader
i can add offset for all bios,but power offset only affected to nitro+ card,not for nitro

Do you know proper way to move UEFI/GOP data?
It seems some bioses (https://www.techpowerup.com/vgabios/190177/190177 for example)
do not have bytes which could be to thrown out to fix UEFI/GOP offset.

doktor83

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Activity: 2548

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Quote from: dallase on April 06, 2017, 01:36:19 PM

Quote from: laik2 on April 06, 2017, 06:34:44 AM

Quote from: doktor83 on April 06, 2017, 05:46:02 AM

that card has samsung mem so copy 1750 to 2000

there is tRAS value different from 0 so its either elpida or micron.

he clearly stated it was Elpida.

He edited his post, but doesnt matter, its not samsung Cheesy

dallase

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Activity: 129

Merit: 10

Quote from: laik2 on April 06, 2017, 06:34:44 AM

Quote from: doktor83 on April 06, 2017, 05:46:02 AM

that card has samsung mem so copy 1750 to 2000

there is tRAS value different from 0 so its either elpida or micron.

he clearly stated it was Elpida.

bardacuda

sr. member

Activity: 430

Merit: 254

Quote from: Zorg33 on April 06, 2017, 07:27:08 AM

There's been HBM mentioned earlier before in this topic....

I got my hands on my first card with HBM (Sap Fury Nitro).

It's behaviour is f@ckin magic! Totally different from GDDR5.

I got ideas from modded Nano and Fury X roms from the OCN thread and copied 400 timings to 500&600.
But nothing changed even a bit, although I copied the straps to both 00 & 01 tables! The hashrates remained exactly the same.

I discovered there is a much more complex mechanism that determines timings dynamically.
Clearly there are frequency ranges about ~20MHz wide, where the timings change gradualy.
I found a sweet spot where I get above 33mh with stock timing, but there is much more I think.
And also there is a strong connection between GPU&HBM freqs, the performance gain is not linear.

And what is with that 100MHz first strap? (There are straps for 100, 400, 500, 600)

So many questions...so much pain..!?

Get on it! I wanna be ready for Vega Grin

niko2004x

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Activity: 126

Merit: 10

Quote from: laik2 on April 06, 2017, 01:03:57 AM

Quote from: zeftcool on April 06, 2017, 12:53:32 AM

00 8D ** 00 VDDC control
work for nitro+ card but not work for nitro card

It works for all which bios can be opened with atombiosreader. I had only one XFX that didn't have(or couldn't find it) VOI.

Most rx 460, a lot rx 470 from XFX and some rx 480 from Powercolor/XFX do not have i2c part in VoltageObjectInfo.

Topic: Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED - page 33. (Read 155645 times)