The unknown aspect is how FPGA are able to adapt to potential resistance from coins/Devs who will fork. The Phi/Lux will be probably be the first case.
I hope they come to realize that the FPGA can provide them with asic resistance by increasing the NRE requirements for ASIC production. With the greater network hashrates higher tech levels of asic will not be nearly as profitable, if at all. It'll push the cost for a secret ASIC to 32, 28, 20nm or lower tech levels. All secret high level asics would be useless (and possibly may operate at a loss on networks secured by fpga). The fpga makes investment risk higher, probability of mask failure higher, time to market longer, and greater probability returns will be lower than expected for the secret asic.
In addition, the rapid reconfiguration of the FPGA via coding allows the FPGA to follow forks if it's ever necessary (to avoid a 16nm asic for instance). In addition, we're more than happy to work with coin devs to create new algos that would be FPGA optimized making use of the unique features of the FPGA to full potential. We do have academics on staff who have already created algos (some of which are used today globally in banking, etc). The failure of most coin devs is that they don't understand hardware. They just keep adding layers of complexity and hoping for the best. We can provide that hardware expertise which they lack.
We could have continued operating in secret. But we've opened up, we've been very open with how many boards are shipping, when, etc. Our goal is to reduce costs to make FPGA even more desirable for the crypto markets. I have been working Xilinx very hard to get pricing down to GPU levels. To do this, it requires moving FPGA in GPU levels.