Topic: First Look at BFL's ASIC Hardware - page 3. (Read 16130 times)
neat
I didnt notice it either....
FRIST, man
FRIST
FRIST
How that gets passed anyone is beyond me.
FRIST, man
FRIST
FRIST
*Folds arms*
*Raises eyebrow*
*Taps foot*
...
*smacks P_shep* *Raises eyebrow*
*Taps foot*
...
Running 8x of the chips at full speed (5Gh/s) and voltage in the SC Single then under-volting and under-clocking 1x of the chips in the Jalapeno makes perfect sense from a thermal (heat) perspective. I think the Single will have a large heatsink and fan similar to the current FPGA Singles while the Jalapeno will have a tiny heatsink and no fan. It's all about the heat and how to get rid of it.
I thought about that too and it makes sense. Perhaps a "full" peno would have gotten a little too hot and would have required a fan? To keep the low-end device simple(r), they decided to underclock it.
*Folds arms*
*Raises eyebrow*
*Taps foot*
...
*Raises eyebrow*
*Taps foot*
...
Crazyates,
Fix the god-damned title. It's pissing me off now.
Fix it to what? I just quoted it to the title of the article the pictures came from. Fix the god-damned title. It's pissing me off now.
Crazyates,
Fix the god-damned title. It's pissing me off now.
Fix the god-damned title. It's pissing me off now.
Mark my words. This is a scam.
Are you a GPU miner about to lose your investment?
/ontopic
I understand the CPU clocking explanations given, but isn't the manufacturing process something that yields predictable results? Ok, let's say there are some rejection rates of ... 1%?
I was expecting the jala to be a full working ASIC chip, the Single to be X working chips and so on. The difference in price between them would be from:
(++) additional materials used (i.e. fan, more electronic components, more metal in the case)
(--) discount from buying "chips in bulk".
Not from dwarfing a chip down.
Code:
Diode ?? uses
Diode ?? uses
SMD ???? jack ?? uses
Switching regulator ?? uses
For 2.2uH inductor use
Code:
Diode to use: CMS05
Diode to use: SS3P4
SMD Barrel jack to use: PJ-003B-SMT
Switching regulator to use: ST1S30
For 2.2uH Inductor, use: IHLP3????
Nothing incredibly valuable here, but it's relatively interesting:
CMS05 Schottky Diode (could be a CMS03)
http://www.digikey.com/product-detail/en/CMS05(TE12L,Q,M)/CMS05QMCT-ND/871536
SS3P4 Schottky Diode
http://www.digikey.com/product-detail/en/SS3P4L-M3%2F86A/SS3P4L-M3%2F86AGITR-ND/2048204
PJ-003B-SMT
http://www.digikey.com/product-detail/en/PJ-003B/CP-003B-ND/96972
ST1S30 Buck Regulator
http://www.digikey.com/product-detail/en/ST1S30IPUR/497-11048-1-ND/2571073
2.2uH Inductor something like: IHLP3232DZER3R3M01 (specific is not that important)
http://www.digikey.com/product-detail/en/IHLP3232DZER3R3M01/541-1373-2-ND/2657469
Running 8x of the chips at full speed (5Gh/s) and voltage in the SC Single then under-volting and under-clocking 1x of the chips in the Jalapeno makes perfect sense from a thermal (heat) perspective. I think the Single will have a large heatsink and fan similar to the current FPGA Singles while the Jalapeno will have a tiny heatsink and no fan. It's all about the heat and how to get rid of it.
Remember, the Jalapeno only needs to dissipate ~5W of heat. Not a lot of heat to even worry about getting rid of.
Running 8x of the chips at full speed (5Gh/s) and voltage in the SC Single then under-volting and under-clocking 1x of the chips in the Jalapeno makes perfect sense from a thermal (heat) perspective. I think the Single will have a large heatsink and fan similar to the current FPGA Singles while the Jalapeno will have a tiny heatsink and no fan. It's all about the heat and how to get rid of it.
This is also a good strategy for yield improvement. Why do you think Intel, AMD and nVidia have different speed bins for their chips? They would love to have all of their chips run at 4GHz or (much) higher but this is not how chip production works. Instead, there is a distribution curve of varying speeds in any given "lot" (or batch) of chips. Some are faster than average, others are slower. The Jalapeno allows BFL to sell chips that are fully functional but not quite fast enough for the SC Single or SC mini-rig performance points. (If anyone asks I can elaborate on this further.)
Marketing and price / performance points are also a factor I assume. (For example, why have a $149 price point at all? The current "low end" of the BFL product line it roughly 4x that. Why not keep the cheapest price in the $500 to $600 range? A: Marketing.)
This is also a good strategy for yield improvement. Why do you think Intel, AMD and nVidia have different speed bins for their chips? They would love to have all of their chips run at 4GHz or (much) higher but this is not how chip production works. Instead, there is a distribution curve of varying speeds in any given "lot" (or batch) of chips. Some are faster than average, others are slower. The Jalapeno allows BFL to sell chips that are fully functional but not quite fast enough for the SC Single or SC mini-rig performance points. (If anyone asks I can elaborate on this further.)
Marketing and price / performance points are also a factor I assume. (For example, why have a $149 price point at all? The current "low end" of the BFL product line it roughly 4x that. Why not keep the cheapest price in the $500 to $600 range? A: Marketing.)
Why does it matter?
Doesn't matter that much but it helps managing expectations and perceptions/perceived value. Something BFL could use some more 
What is the practical difference between a "full working ASIC" chip and "dwarfing a chip down" if they both mine at 3.5 GH/s? Why do you care?
Why does it matter?
Doesn't matter that much but it helps managing expectations and perceptions/perceived value. Something BFL could use some more What is the practical difference between a "full working ASIC" chip and "dwarfing a chip down" if they both mine at 3.5 GH/s? Why do you care?
That is fine with the smileys and all... as long as you realize these expectations are unrealistic and far beyond what major chipmakers like AMD and Intel guarantee.
Why does it matter?
Doesn't matter that much but it helps managing expectations and perceptions/perceived value. Something BFL could use some more What is the practical difference between a "full working ASIC" chip and "dwarfing a chip down" if they both mine at 3.5 GH/s? Why do you care?
Why does it matter?
Doesn't matter that much but it helps managing expectations and perceptions/perceived value. Something BFL could use some more
What is the practical difference between a "full working ASIC" chip and "dwarfing a chip down" if they both mine at 3.5 GH/s? Why do you care?
Why does it matter?
Doesn't matter that much but it helps managing expectations and perceptions/perceived value. Something BFL could use some more
Mark my words. This is a scam.
Are you a GPU miner about to lose your investment?
/ontopic
I understand the CPU clocking explanations given, but isn't the manufacturing process something that yields predictable results? Ok, let's say there are some rejection rates of ... 1%?
I was expecting the jala to be a full working ASIC chip, the Single to be X working chips and so on. The difference in price between them would be from:
(++) additional materials used (i.e. fan, more electronic components, more metal in the case)
(--) discount from buying "chips in bulk".
Not from dwarfing a chip down.
Mark my words. This is a scam.
Are you a GPU miner about to lose your investment?
/ontopic
I understand the CPU clocking explanations given, but isn't the manufacturing process something that yields predictable results? Ok, let's say there are some rejection rates of ... 1%?
I was expecting the jala to be a full working ASIC chip, the Single to be X working chips and so on. The difference in price between them would be from:
(++) additional materials used (i.e. fan, more electronic components, more metal in the case)
(--) discount from buying "chips in bulk".
Not from dwarfing a chip down.
It depends on if BFL plans on using semi-defective chips with a crippled pipeline or simply reduced clockspeed. It's entirely possible that the Jalapenos may be using full speed capable ICs but we won't really know until someone gets their hands on one and wants to risk damaging it to probe around the board and figure out what BFL has done.
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