First Look at BFL's ASIC Hardware - page 5.

KIDC

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Quote from: fcmatt on September 25, 2012, 08:49:22 PM

Sept 25th... And they show design pics. This would not be allowed on kickstarter.com now days to raise cash.
Ship date.. Hm.. A ways away me thinks. Jan 2013 seems about right.

Well, for me and other BFL customers I hope you're wrong. I did have this thought as well as was going to post the same. One rendering that may have been made a while ago may not be indicative of a delay, as they may have long since moved past that rendering and on to testing of an actual prototype. You make a good point though. With about 45 days left until they're supposed to be delivering product it does make oneself a little concerned if all they've done is just a couple of 3D renders of said product.

Then again, I have no experience in electrical engineering or ASIC design so perhaps this type of emulation and mockup process is the normal procedure.

KIDC

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Quote from: DeathAndTaxes on September 25, 2012, 08:31:02 PM

Quote from: tytus on September 25, 2012, 05:41:16 PM

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

USB is 5V and max current is 0.5A = 2.5W per port.
Dual USB ports = 5 watts.

Laptop CD ROM drives have been doing that trick for years.

Even if it is two USB ports 80 watts is still fantastic. 500 Mhash/watt? Yes please.

fcmatt

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Sept 25th... And they show design pics. This would not be allowed on kickstarter.com now days to raise cash.
Ship date.. Hm.. A ways away me thinks. Jan 2013 seems about right.

DeathAndTaxes

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Gerald Davis

Quote from: tytus on September 25, 2012, 05:41:16 PM

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

USB is 5V and max current is 0.5A = 2.5W per port.
Dual USB ports = 5 watts.

Laptop CD ROM drives have been doing that trick for years.

Cablez

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I owe my soul to the Bitcoin code...

Aw come on, at least give us the whole deal: http://www.youtube.com/watch?v=4pXfHLUlZf4

BOT: Looks real promising for BFL.

KIDC

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Bogart

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Quote from: P_Shep on September 25, 2012, 04:05:23 PM

of course if the yeild is so high they use full speed capable chips in the Jally, then those lucky people could up-clock it back to 5Gh/s.

I'm thinking though, rather then down-clock, they might disable hash-cores. (my thinking is the chip will work by having 1000's of individual hashing cores working simultaneosly)

Consider that a 5850 is a 5870 with one of its 10 shader groups disabled. A 5830 is the same with 3 groups disabled. I think they may be clocked lower also.

AMD laser cuts the traces so there is no hope of "unlocking" them.

SgtSpike

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Quote from: P_Shep on September 25, 2012, 05:42:50 PM

Quote from: tytus on September 25, 2012, 05:41:16 PM

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

2.5W for USB 2.0

Was just going to mention that...

500ma @ 5v = 2.5W

Extrapolating that, if we assume that a 3.5GH/s chip will take up half of the electricity of a 5GH/s chip (power consumption goes up exponentially with speed increase), then a single would use, at max:

2.5W x 2 x 8 = 40 watts.

Interesting...

P_Shep

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This is not OK.

Quote from: tytus on September 25, 2012, 05:41:16 PM

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

2.5W for USB 2.0

tytus

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USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

Dexter770221

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My assumption was 10 chips @ 4GH/s each. In Jally 1 chip downclocked and downvolted just to met USB power specs. I wasn't wrong that much Wink

From my perspective it's oversized and overengeenered. It can be done much more simpler than that.

P_Shep

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This is not OK.

of course if the yeild is so high they use full speed capable chips in the Jally, then those lucky people could up-clock it back to 5Gh/s.

I'm thinking though, rather then down-clock, they might disable hash-cores. (my thinking is the chip will work by having 1000's of individual hashing cores working simultaneosly)

jgarzik

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Quote from: AmDD on September 25, 2012, 03:39:11 PM

I guess i was really leaning more towards the idea of "Could we 'unlock' the jally and bump it up to 5Ghs? Or 4Ghs?

And the answer is probably predictable (I'm guessing, no inside info): "yes, but you void your warranty, fry your hardware, and have to deal with lockups"

AmDD

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Totally agree. I wasnt implying that they would "cheat" us or anything. more of a serious question as to how they would lower the hash rate. Would it be lowering the clock speed? hardware side? firmware? Possibly software/protocol?

I guess i was really leaning more towards the idea of "Could we 'unlock' the jally and bump it up to 5Ghs? Or 4Ghs?

P_Shep

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This is not OK.

Maybe chips with flaws (they'll always be some in a batch) will be used for the Jally, Just like CPUs are tested then binned to run at certain speeds.

jgarzik

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Quote from: AmDD on September 25, 2012, 03:21:36 PM

Quote from: fcmatt on September 25, 2012, 03:13:30 PM

40 gh/s divided by 8 asic chips is 5 gh/s per chip.

so the jally will be crippled to only run at 3.5 gh/s or worse?

BFL has been saying 3.5Ghs from the beginning, this is no surprise. How exactly they plan on doing this is a different tale...

After big chip makers like AMD or Intel manufacture a chip, they run it through production quality control testing. A chip that is theoretically the same as another chip may exhibit different behaviors under stress. As a result, some chips in a batch may be binned and sold as 3 Ghz chips. Other chips in the same batch, that did not perform as well in testing, may be binned and sold as 1.5 Ghz chips.

It is very realistic and following standard commercial practices that the same chips from the same batch might run at slightly different clock speeds, to avoid manufacturing imperfections or whatnot.

So perhaps Jalapeno units are 5 Ghash/sec that did not pass quals at top speed, but do pass quals at lower speeds.

Any sort of scenario like this is possible, standard for chip manufacturing, and not "cheating."

AmDD

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Quote from: fcmatt on September 25, 2012, 03:13:30 PM

40 gh/s divided by 8 asic chips is 5 gh/s per chip.

so the jally will be crippled to only run at 3.5 gh/s or worse?

BFL has been saying 3.5Ghs from the beginning, this is no surprise. How exactly they plan on doing this is a different tale...

fcmatt

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40 gh/s divided by 8 asic chips is 5 gh/s per chip.

so the jally will be crippled to only run at 3.5 gh/s or worse?

Glasswalker

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Where's the Flux Capacitor Damnit!?!?!

What good is the blinky little box if I can't line 1.21 Jiggawatts of lightning into it and hash like it was the 80s!

Nolo

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Whoa, there are a lot of cats in this wall.

Ooooh.....Ahhhhh.... Grin

Topic: First Look at BFL's ASIC Hardware - page 5. (Read 16130 times)