Damn! 451 peak!
I wonder if there is a way to increase the average speed (ie shorten the gap between the peak and the minimum). 400 Mh/s average would be really sweet to have.
Topic: FPGA development board "Icarus" - DisContinued/ important announcement - page 37. (Read 207279 times)
January 16, 2012, 01:45:16 AM
Damn! 451 peak!
I wonder if there is a way to increase the average speed (ie shorten the gap between the peak and the minimum). 400 Mh/s average would be really sweet to have.
January 16, 2012, 01:16:11 AM
Hi
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]
[1]----
ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx
Answers database for "ERROR:Pack:198" and read the Master Answer Record for
MAP Trimming Issues.
Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 422
Process "Map" failed
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]
[1]----
ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx
Answers database for "ERROR:Pack:198" and read the Master Answer Record for
MAP Trimming Issues.
Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 422
Process "Map" failed
do you copy the "sha256_top.ngc" NGC file(first step you got) to the 2nd step "right_with_bigID_and_ZERONonceMod2" folder?
January 16, 2012, 01:12:04 AM
Hi
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]
[1]----
ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx
Answers database for "ERROR:Pack:198" and read the Master Answer Record for
MAP Trimming Issues.
Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 422
Process "Map" failed
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]
[1]----
ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx
Answers database for "ERROR:Pack:198" and read the Master Answer Record for
MAP Trimming Issues.
Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 422
Process "Map" failed
January 16, 2012, 12:31:30 AM
wow great job!
January 14, 2012, 02:32:41 PM
January 12, 2012, 10:21:39 PM
it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.
I have been very happy with this approach.
The only stuff you need on the daughterboard are the .47/4.7 caps and the FPGA (I've moved the clock and 100uF caps to the motherboard but haven't taken new photos). Putting everything else on a different board means that you can continue improving the "other stuff" and upgrade later without having to reball a 484-pin BGA chip.
Just make sure that the inter-board connectors can carry the massive amount of current that the 1V2 rail pulls...
I like your approach eldentyrell. Speaking of which I asked you on the thread if you were still thinking of selling your boards, but you never replied. Have you decided that it's not really worth your time marketing your boards?
Sorry btw for the cross-thread pollution.
January 12, 2012, 10:01:02 PM
it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.
I have been very happy with this approach.
The only stuff you need on the daughterboard are the .47/4.7 caps and the FPGA (I've moved the clock and 100uF caps to the motherboard but haven't taken new photos). Putting everything else on a different board means that you can continue improving the "other stuff" and upgrade later without having to reball a 484-pin BGA chip.
Just make sure that the inter-board connectors can carry the massive amount of current that the 1V2 rail pulls...
January 12, 2012, 11:25:20 AM
8 package, 16 Icarus are on the way. delivery with reinforced packaging. all payed buyer's product is on the way.
i will send them to EMS agent tomorrow.
Xiangfu already received the first 3 boards today, we are in the same city.
Really? Is this due to high manufacturing costs of board with more than 1 FPGA? Or?
When you say daughter - mother architecture you mean to say that you'll have one mother board and several expansion slots (aka daughter boards) into which one can plug several (how many?) daughter boards?
I would really like to see a nice fpga cluster geared solution - a nicely done backplane with several (10+) spots to plug in daughterboards that will each have either 1 or 2 fpga per daughterboard
i'm still thinking...
January 12, 2012, 09:27:52 AM
that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT. 
Shows what I know. I should have recognized that by it's color. :/ Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days. Edge would be nice. Atleast no one can accuse you of wasting edge space though. =)
I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available?
Cheers,
Derek
it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.
Really? Is this due to high manufacturing costs of board with more than 1 FPGA? Or?
When you say daughter - mother architecture you mean to say that you'll have one mother board and several expansion slots (aka daughter boards) into which one can plug several (how many?) daughter boards?
I would really like to see a nice fpga cluster geared solution - a nicely done backplane with several (10+) spots to plug in daughterboards that will each have either 1 or 2 fpga per daughterboard
January 12, 2012, 08:20:48 AM
that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.
Shows what I know. I should have recognized that by it's color. :/ Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days. Edge would be nice. Atleast no one can accuse you of wasting edge space though. =)
I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available?
Cheers,
Derek
it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.
January 12, 2012, 07:51:34 AM
that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.
Shows what I know. I should have recognized that by it's color. :/ Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days. Edge would be nice. Atleast no one can accuse you of wasting edge space though. =)
I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available?
Cheers,
Derek
January 12, 2012, 07:13:43 AM
Hmm, I'm a bit concerned about this: http://en.qi-hardware.com/wiki/File:Icarus_Soldering.capacitance_problem.JPG
oh, it looks like this capacitor is touched by some stuff during the transport.
it there any issues except the skew?
and:
i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor.
and and:
looks like i must open the package again and do some reinforce to the package...
I highly doubt that capicitor is in any way damaged. Maybe if it got 'shoved' down on its pins or something, then maybe.
However, that resistor looks a lil funky.
that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.
January 12, 2012, 07:01:53 AM
Hmm, I'm a bit concerned about this: http://en.qi-hardware.com/wiki/File:Icarus_Soldering.capacitance_problem.JPG
oh, it looks like this capacitor is touched by some stuff during the transport.
it there any issues except the skew?
and:
i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor.
and and:
looks like i must open the package again and do some reinforce to the package...
I highly doubt that capicitor is in any way damaged. Maybe if it got 'shoved' down on its pins or something, then maybe.
However, that resistor looks a lil funky.
January 12, 2012, 06:36:03 AM
Hmm, I'm a bit concerned about this: http://en.qi-hardware.com/wiki/File:Icarus_Soldering.capacitance_problem.JPG
oh, it looks like this capacitor is touched by some stuff during the transport.
it there any issues except the skew?
and:
i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor.
and and:
looks like i must open the package again and do some reinforce to the package...
January 12, 2012, 06:27:22 AM
Hmm, I'm a bit concerned about this: http://en.qi-hardware.com/wiki/File:Icarus_Soldering.capacitance_problem.JPG
Looks like a transport damage to me ?
January 12, 2012, 05:51:00 AM
Hmm, I'm a bit concerned about this: http://en.qi-hardware.com/wiki/File:Icarus_Soldering.capacitance_problem.JPG
What? That's Chinese high quality assembly! On a more serious note, as long as the solder joint is ok a electrolytic cap sitting a bit crooked won't affect anything other than looks.
LOL.
I think that is fine. Won't affect anything much.
January 12, 2012, 05:44:05 AM
Hmm, I'm a bit concerned about this: http://en.qi-hardware.com/wiki/File:Icarus_Soldering.capacitance_problem.JPG
What? That's Chinese high quality assembly! On a more serious note, as long as the solder joint is ok a electrolytic cap sitting a bit crooked won't affect anything other than looks.
January 12, 2012, 05:37:06 AM
Hmm, I'm a bit concerned about this: http://en.qi-hardware.com/wiki/File:Icarus_Soldering.capacitance_problem.JPG
January 12, 2012, 04:39:22 AM
Hi
I receive the Icarus that have one big fan on top of cooling plate. checkout here:
http://en.qi-hardware.com/wiki/File:Icarus_Front.JPG
also I created a wiki page about Icarus: 'http://en.qi-hardware.com/wiki/Icarus'
feel free to update the page
I receive the Icarus that have one big fan on top of cooling plate. checkout here:
http://en.qi-hardware.com/wiki/File:Icarus_Front.JPG
also I created a wiki page about Icarus: 'http://en.qi-hardware.com/wiki/Icarus'
feel free to update the page
That is the same sentence to cause me to think that fans are no longer included in the 2nd batch.
January 09, 2012, 11:21:52 PM
when will you start to accept new orders?
after i finish present shipment.
ADD@1/12
i finished packing tonight. but a burst work from school made me very busy these days. i hope can send them out tomorrow.
Jump to: