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Topic: FPGA development board "Icarus" - DisContinued/ important announcement - page 37. (Read 207285 times)

legendary
Activity: 3080
Merit: 1080


Damn! 451 peak!  Shocked

I wonder if there is a way to increase the average speed (ie shorten the gap between the peak and the minimum). 400 Mh/s average would be really sweet to have.
hero member
Activity: 592
Merit: 501
We will stand and fight.
Hi

anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
 1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
     I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?

 2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]

[1]----
ERROR:Pack:198 - NCD was not produced.  All logic was removed from the design.
   This is usually due to having no input or output PAD connections in the
   design and no nets or symbols marked as 'SAVE'.  You can either add PADs or
   'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
   the mapper.  For more information on trimming issues search the Xilinx
   Answers database for "ERROR:Pack:198" and read the Master Answer Record for
   MAP Trimming Issues.

Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   1
Number of warnings : 422

Process "Map" failed



do you copy the "sha256_top.ngc" NGC file(first step you got) to the 2nd step "right_with_bigID_and_ZERONonceMod2" folder?
full member
Activity: 120
Merit: 100
Hi

anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
 1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
     I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?

 2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]

[1]----
ERROR:Pack:198 - NCD was not produced.  All logic was removed from the design.
   This is usually due to having no input or output PAD connections in the
   design and no nets or symbols marked as 'SAVE'.  You can either add PADs or
   'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
   the mapper.  For more information on trimming issues search the Xilinx
   Answers database for "ERROR:Pack:198" and read the Master Answer Record for
   MAP Trimming Issues.

Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   1
Number of warnings : 422

Process "Map" failed

hero member
Activity: 504
Merit: 500
legendary
Activity: 892
Merit: 1002
1 BTC =1 BTC
legendary
Activity: 3080
Merit: 1080
it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.

I have been very happy with this approach.

The only stuff you need on the daughterboard are the .47/4.7 caps and the FPGA (I've moved the clock and 100uF caps to the motherboard but haven't taken new photos).  Putting everything else on a different board means that you can continue improving the "other stuff" and upgrade later without having to reball a 484-pin BGA chip.

Just make sure that the inter-board connectors can carry the massive amount of current that the 1V2 rail pulls...

I like your approach eldentyrell. Speaking of which I asked you on the thread if you were still thinking of selling your boards, but you never replied. Have you decided that it's not really worth your time marketing your boards?

Sorry btw for the cross-thread pollution.
donator
Activity: 980
Merit: 1004
felonious vagrancy, personified
it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.

I have been very happy with this approach.

The only stuff you need on the daughterboard are the .47/4.7 caps and the FPGA (I've moved the clock and 100uF caps to the motherboard but haven't taken new photos).  Putting everything else on a different board means that you can continue improving the "other stuff" and upgrade later without having to reball a 484-pin BGA chip.

Just make sure that the inter-board connectors can carry the massive amount of current that the 1V2 rail pulls...
hero member
Activity: 592
Merit: 501
We will stand and fight.


8 package, 16 Icarus are on the way. delivery with reinforced packaging. all payed buyer's product is on the way.

i will send them to EMS agent tomorrow.

Xiangfu already received the first 3 boards today, we are in the same city.


Really? Is this due to high manufacturing costs of board with more than 1 FPGA? Or?

When you say daughter - mother architecture you mean to say that you'll have one mother board and several expansion slots (aka daughter boards) into which one can plug several (how many?) daughter boards?

I would really like to see a nice fpga cluster geared solution - a nicely done backplane with several (10+) spots to plug in daughterboards that will each have either 1 or 2 fpga per daughterboard Smiley

i'm still thinking... Cheesy
legendary
Activity: 3080
Merit: 1080
that "resistor" infact is a ceramic capacitor. soldered  by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.  Wink

Shows what I know. I should have recognized that by it's color. :/  Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days.  Edge would be nice. Atleast no one can accuse you of wasting edge space though. =)

I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available?

Cheers,
  Derek

it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.

Really? Is this due to high manufacturing costs of board with more than 1 FPGA? Or?

When you say daughter - mother architecture you mean to say that you'll have one mother board and several expansion slots (aka daughter boards) into which one can plug several (how many?) daughter boards?

I would really like to see a nice fpga cluster geared solution - a nicely done backplane with several (10+) spots to plug in daughterboards that will each have either 1 or 2 fpga per daughterboard Smiley
hero member
Activity: 592
Merit: 501
We will stand and fight.
that "resistor" infact is a ceramic capacitor. soldered  by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.  Wink

Shows what I know. I should have recognized that by it's color. :/  Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days.  Edge would be nice. Atleast no one can accuse you of wasting edge space though. =)

I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available?

Cheers,
  Derek

it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.
hero member
Activity: 504
Merit: 500
that "resistor" infact is a ceramic capacitor. soldered  by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.  Wink

Shows what I know. I should have recognized that by it's color. :/  Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days.  Edge would be nice. Atleast no one can accuse you of wasting edge space though. =)

I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available?

Cheers,
  Derek
hero member
Activity: 592
Merit: 501
We will stand and fight.

oh, it looks like this capacitor is touched by some stuff during the transport.
it there any issues except the skew? Huh

and:

i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor. Huh

and and:
looks like i must open the package again and do some reinforce to the package... Grin

I highly doubt that capicitor is in any way damaged. Maybe if it got 'shoved' down on its pins or something, then maybe.
However, that resistor looks a lil funky.  Tongue
i agree with you.
that "resistor" infact is a ceramic capacitor. soldered  by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.  Wink
hero member
Activity: 504
Merit: 500

oh, it looks like this capacitor is touched by some stuff during the transport.
it there any issues except the skew? Huh

and:

i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor. Huh

and and:
looks like i must open the package again and do some reinforce to the package... Grin

I highly doubt that capicitor is in any way damaged. Maybe if it got 'shoved' down on its pins or something, then maybe.
However, that resistor looks a lil funky.  Tongue
hero member
Activity: 592
Merit: 501
We will stand and fight.

oh, it looks like this capacitor is touched by some stuff during the transport.
it there any issues except the skew? Huh

and:

i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor. Huh

and and:
looks like i must open the package again and do some reinforce to the package... Grin
legendary
Activity: 1022
Merit: 1000
BitMinter
hero member
Activity: 518
Merit: 500
What? That's Chinese high quality assembly! Grin
On a more serious note, as long as the solder joint is ok a electrolytic cap sitting a bit crooked won't affect anything other than looks.

LOL. Cheesy

I think that is fine. Won't affect anything much.
sr. member
Activity: 406
Merit: 257
What? That's Chinese high quality assembly! Grin
On a more serious note, as long as the solder joint is ok a electrolytic cap sitting a bit crooked won't affect anything other than looks.
legendary
Activity: 3080
Merit: 1080
full member
Activity: 120
Merit: 100
Hi

I receive the Icarus that have one big fan on top of cooling plate. checkout here:
  http://en.qi-hardware.com/wiki/File:Icarus_Front.JPG

also I created a wiki page about Icarus: 'http://en.qi-hardware.com/wiki/Icarus'
feel free to update the page  Grin

That is the same sentence to cause me to think that fans are no longer included in the 2nd batch.
hero member
Activity: 592
Merit: 501
We will stand and fight.
when will you start to accept new orders?

after i finish present shipment.

ADD@1/12

i finished packing tonight. but a burst work from school made me very busy these days. i hope can send them out tomorrow. Sad
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