maybe after this project, when i have some free time. i will build a small FPGA(LX16 FT256) dev board with DDR2 RAM and FT232 connect as you describe and sell it at a ultra low price(50$) for learning.
As a dev board user I can tell you the following: market is full of single FPGA dev boards. The uniqueness and greatness of your designs (Icarus & Lancelot) lies in them being paired FPGAs with non-trivial interconnectivity. The only problem with them is that they have a bent straw instead of a pipe for the external communication.
I'm even thinking of getting a Lancelot and paying someone to rework the FT232R connections using additional 10 wires soldered to the unpopulated GPIO vias. But this is something above my manual skill and resources, and because of that it will have to wait.
If you ever find a need to do Lancelot v2 (like Icarus v2) then just please remember to route all the available signals from the comm chip to the FPGA.
And for your future designs please consider using the high-speed USB chips instead of full-speed USB and having one comm pipe per FPGA. So the Lancelot v5 would have FT2232H (dual high-speed USB). The market for the multi-FPGA boards its there already:
https://bitcointalksearch.org/topic/m.973019I just realised that I have given such a pitch already years ago. I was an early advocate of dual Pentium (Classic) and dual Celeron (with SMP mod) motherboards. Those who listened were very well prepared for the arrival of multicore CPUs. Something similar will happen with FPGAs.
Assume that FPGA is configured for loopback only and not for any work. Did you test that the FT232R works reliably at the full 3Mbps serial communication speed?
