) if you have any.When that new bitstream will be achievable?
Topic: FPGA development board "Lancelot" - accept bitsteam developer's orders. - page 7. (Read 101887 times)
September 18, 2012, 06:29:12 AM
For those who ordered dev kit. There's trojan (Dynamer) on USB stick in file patch.exe, Altium Designer folder. Microsoft Security Essential reports that way. Don't have other antiviruses, so please confirm (or confirm that is not ) if you have any.
When that new bitstream will be achievable?
) if you have any.When that new bitstream will be achievable?
September 18, 2012, 02:44:25 AM
So If I understand this correctly, we can expect a new bitstream for our Lancelots very soon ?
September 17, 2012, 05:14:27 AM
ngzhang - send me one when you have them working and I'll have cgminer code hashing on it as fast as possible ready for release to the general public 
LAN or WiFi connection. No PC needed. But only 100MH/W thats the nail to coffin for this project...
Can wait to test new btstream
i noticed that nobody mentioned power consume value at this time. so i decide to remove that rough estimate value too. September 17, 2012, 04:55:15 AM
ngzhang - send me one when you have them working and I'll have cgminer code hashing on it as fast as possible ready for release to the general public
LAN or WiFi connection. No PC needed. But only 100MH/W thats the nail to coffin for this project...
Can wait to test new btstream
September 16, 2012, 09:46:17 PM
http://i.minus.com/itzBd3W9qEQXQ.jpg
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
According rumors from Chinese source. Mr. Zhang is developing ASIC miners each running at 60 Ghash/s for US$1400. Existing Iracus and Lancelot users could sell their devices back (Iracus=$300, Lancelot=$400) in exchange for the new ASIC miner.
Would be a pity to get rid of them now that I can even mess with programming them in the distant future since I bought the dev kit ...
... though as I have mentioned to other ASIC developers
ngzhang - send me one when you have them working and I'll have cgminer code hashing on it as fast as possible ready for release to the general public
September 16, 2012, 09:33:50 PM
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
According rumors from Chinese source. Mr. Zhang is developing ASIC miners each running at 60 Ghash/s for US$1400. Existing Iracus and Lancelot users could sell their devices back (Iracus=$300, Lancelot=$400) in exchange for the new ASIC miner.
September 16, 2012, 07:56:48 PM
What is a large amount of money? 100k?
September 16, 2012, 04:05:55 PM
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
September 16, 2012, 03:43:47 PM
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
if you have large amount of money, please pay more attention.
I like ngzhang's style.
Quoted just because of so much win!!!
September 16, 2012, 01:49:41 PM
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
if you have large amount of money, please pay more attention.
I like ngzhang's style.
September 16, 2012, 12:36:15 PM
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
if you have large amount of money, please pay more attention.
Thank you ngzhang. That means your developing fpga nightmare is over, right?
September 16, 2012, 12:20:49 PM
Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
September 11, 2012, 03:43:09 PM
Ngzang,
Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?
Best
Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?
Best
CPU power is not a big problem there.
Ngzhang,
And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?
And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?
a semiconductor cooling chip will significantly improve the speed （if we finally implement the auto speed adjust feature), but will cause a huge energy consumption.
September 11, 2012, 07:19:16 AM
Ngzhang,
And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?
And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?
September 11, 2012, 04:57:00 AM
Ngzang,
Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?
Best
Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?
Best
September 11, 2012, 04:49:40 AM
Wow, great job. Looks really dense 64 cycle 2 stage core?
64 cycle 2 stage core?yeah， every 64cycle pre bitcoin hash.
present we must place the other half chip... the same work as the first half, but the stupid tool is getting stuck. nobody could imagine the difficulty unless they made similar work before.
September 11, 2012, 04:25:48 AM
Wow, great job. Looks really dense 64 cycle 2 stage core?
64 cycle 2 stage core? September 11, 2012, 03:12:45 AM
and this is 40 64cycle cores @ ~4ns...
Wait.
40x64 cycles cores @ 250Mhz = 20xfull hashers @250Mhz = 5GH/s per chip
Who needs ASICs, really ...
finally will be 80cores there, maybe 70+ at first.
speed = core amount / 64 * freq
but i think we will face same power issues when impact the high frequency. but i think 250MHs pre chip at first and 350MHs after carefully optimization is a optimistic estimate.
on XILINX -7 series, it will get a 30% better core density (means: use 30% less luts for a single core), and at least 50% frequency improve. means ~ 800-1G hash pre XC7A200T chip. this performance is close to a normal 0.11~0.13 um ASIC. the cost consist in sales volume.
I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html
Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is deadhttp://www.bitfury.org/xc6slx150.html
yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.
Sometimes I feel the FPGA development world could benefit massively from clean-slate-designed open source tools to do the logic synthesis, mapping, placement, routing, etc.
Right now, there is not much competition between Xilinx and Altera to improve their software tools, because the competition is mostly centered around the hardware capabilities of their chips, not the quality of the software stack.
if you are a " VOL customer", XILINX will open more bottom layer information and give you more support. then you could implement wanted substructures.
September 11, 2012, 01:30:12 AM
and this is 40 64cycle cores @ ~4ns...
Wait.
40x64 cycles cores @ 250Mhz = 20xfull hashers @250Mhz = 5GH/s per chip
Who needs ASICs, really ...
September 10, 2012, 10:21:14 PM
I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html
Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is deadhttp://www.bitfury.org/xc6slx150.html
yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.
Sometimes I feel the FPGA development world could benefit massively from clean-slate-designed open source tools to do the logic synthesis, mapping, placement, routing, etc.
Right now, there is not much competition between Xilinx and Altera to improve their software tools, because the competition is mostly centered around the hardware capabilities of their chips, not the quality of the software stack.
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