https://hashfast.com/hello-world/
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Things are moving quickly! We finally have the first Golden Nonce chip, we began testing it —sending the first current through the 28nm chip to see how it performs. So far, things are looking very good. HashFast co-founder and CTO Simon Barber to give us the play-by-play of the first tests.
We brought up IOVdd first. Up to 1.8V — draws less than the minimum 10mA the bench supply reads.
Next core. Something odd was observed here. Initially, we saw high current draw as we brought the voltage up, reaching 0.7V where it was drawing 2.5A. As the voltage increased a little over 0.7v the current suddenly dropped to 82mA. It stayed there up to Vddcore=0.8v. This odd pattern of high current at low core voltage was repeatable. RST held low. MODE and BYPASS were held high. PLLVdd pulled to Vdd. All other inputs seemed to float low, with a 1Mohm impedance probe.
Next CLK was applied — first 37Hz. 4mA increase in Vdd core current. Took chip out of reset. No change. Next increase clock speed, this increases current. In a couple of steps, we got it to 6Mhz, where the core Vdd was drawing 548mA.
After a few minutes, we turned things off. On retrying, we didn’t find the same odd, high current during ramp of core Vdd. Perhaps this was due to CLK floating then, and not since?
Calling it a night, having trouble getting the serial port levels shifted correctly. Will continue in the morning.
— Simon
Over the next few days, the HashFast engineering team will be working intensely as they subject the GN to more tests. As we’re able to get them to break and give us an update, we’ll let you know how it’s going.
Simon will also be tweeting on the HashFast account — if you’re interested in seeing the results as the they come, follow us @HashFast on Twitter.
We brought up IOVdd first. Up to 1.8V — draws less than the minimum 10mA the bench supply reads.
Next core. Something odd was observed here. Initially, we saw high current draw as we brought the voltage up, reaching 0.7V where it was drawing 2.5A. As the voltage increased a little over 0.7v the current suddenly dropped to 82mA. It stayed there up to Vddcore=0.8v. This odd pattern of high current at low core voltage was repeatable. RST held low. MODE and BYPASS were held high. PLLVdd pulled to Vdd. All other inputs seemed to float low, with a 1Mohm impedance probe.
Next CLK was applied — first 37Hz. 4mA increase in Vdd core current. Took chip out of reset. No change. Next increase clock speed, this increases current. In a couple of steps, we got it to 6Mhz, where the core Vdd was drawing 548mA.
After a few minutes, we turned things off. On retrying, we didn’t find the same odd, high current during ramp of core Vdd. Perhaps this was due to CLK floating then, and not since?
Calling it a night, having trouble getting the serial port levels shifted correctly. Will continue in the morning.
— Simon
Over the next few days, the HashFast engineering team will be working intensely as they subject the GN to more tests. As we’re able to get them to break and give us an update, we’ll let you know how it’s going.
Simon will also be tweeting on the HashFast account — if you’re interested in seeing the results as the they come, follow us @HashFast on Twitter.
it sound's scary to me. they have how many weeks left until the end of the year?
?!!!!!!
