Topic: HashFast announces specs for new ASIC: 400GH/s - page 529. (Read 880816 times)

sounds legit to me, lets see and hope the best 

they can't divulge that stuff.  you should know better.  what good would it do giving it to some random internet guy who could actually be a competitor.

you're right in that delivery is going to be close.  but even KNC was/is late.

Not that we don't believe you about having already sourced the boards and cases.  Can you divulge who is providing these services for you?  Who is doing your board manufacturing?  Who is doing your board assembly?  Who is doing your system integration.

Seems to me like you won't hit October, as promised.

IOW, even in the best case scenario,  "october" shipments almost certainly wont happen before november.
But everything is on track .

To be more verbose...

Similar to what we did with Uniquify, we have been working extremely closely with both the board manufacturer / assembly house, and with the company that will be assembling the finished Baby Jets and Sierras. We are in daily, often hourly contact with them.
 
I'll request pix.

some pics?

there is a great chart out there called a Waterfall.  i've seen several versions of it as it's been updated routinely by TSMC.

i've tried to get them to show it to you guys but apparently there's something proprietary about it.  if you saw it, it'd knock your socks off as it relates to the competition.

Yes.

Are the boards and cases sourced already for the chips to be assembled into?

LOL - fixed.  I guess if I'm trying to make a sarcastic remark, I should get my numbers the right-way-around....

remember we are dealing with a TSMC rocket launch which is the best in the industry. 

if they can't get it done, no one can.

The back end of line tends to go significantly faster than the front end of line.

That said. It took a week longer to tape out than we had hoped. (This kind of thing happens a lot in the world of asics.) So yes: we'd hoped to have silicon out of fab in mid October, and now it's looking like late October. Again, we cannot go into more detail than that, due to the preferences of our foundry.

Then, once the silicon is out, we are doing everything we can (including hand-carrying silicon wafers from foundry to the next steps, in Silicon Valley) to get product to our customers as quickly as possible. Best case scenario is five days from wafers-out-of-fab to boot up of the first Baby Jet.

- Amy

Actually, it's around 2. Anyway, is there a table describing these steps out there? I suppose them to be on time, and that the second half of the steps is faster to go trough than the first half.

And 128/247 is approximately 1/2 for those of you that can't do math...

What he is saying is that they are halfway done in making the chips, lol. For those of you who can't read between the lines.

They may be on schedule but it seems awfully aggressive for finished devices that are supposed to beginning shipping out in just 11 days. I really hope they make their target, especially since I have one of the first baby jets ordered.

no i am not.

i just believe i'm in the right camp for the long run.

Thanks, Amy.  I feel smarter already.
@Cypherdoc:  I take it you're still on the payroll?

So, even though you can't say anything, I would guess that you're roughly at about step 128 of 247 total....

For those of you wondering how things are going with our chip fabrication, the answer is: Quite well. Everything at the foundry is on schedule (which believe me we are watching like a hawk every day!)

Unfortunately, our agreements with TSMC forbid us going into much, if any, detail about where exactly in the process our wafers are. 'Cause that would be telling.

On the other hand, nothing forbids me writing a general educational article on semiconductor fabrication.

And today, I'd like to introduce you to Front End of Line (FEOL) and Back End of Line (BEOL) fabrication. And the moment in between, when a foundry switches from one to the other.

Front End of Line is the first half of the process, where all the transistors are created.

"FEOL processing refers to the formation of the transistors directly in the silicon. Some steps include growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties."  -- Wikipedia

Back End of Line is the second half of the process, where those transistors are wired up together. An insulating layer is deposited, metal wiring created on top of it, then another layer of insulation, and vias - metal tunnels - to connect layers. They form the wiring that connects the transistors.

"BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing [metal] in them. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections."

The point when the first half of the process (FEOL) is done, and the second begins (BEOL), is an entirely artificial but highly satisfying milestone on the way to finished chips.

Some call it 'Contact', some call it the start of metallization, some just call it progress.

And thus ends my lesson on generic semiconductor manufacturing practices!

** You can read more about semiconductor fabrication here: http://en.wikipedia.org/wiki/Semiconductor_fabrication

For more or less these same words on our blog, you can look here: http://www.hashfast.com/blog

 

well, i'm not as annoyed as you might want me to be. 

it's just that they asked me to pre-announce yesterday afternoon with the expectation that they'd f/u within a short time period.  no biggie.  it's coming soon.