Another source: http://www.altera.com/technology/system-design/articles/2012/20nm-systems-era.html
Perhaps no semiconductor process has generated more controversy—before a single product has been shipped—than the 20 nm node. There was argument over whether the node would have to wait for production-ready EUV lithography. It did not: double-patterning, though expensive and restrictive on layout, has met the needs of the finest-resolution mask layers.
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The 20 nm node is arguably the most difficult ever attempted for production, and just a description of the technical challenges would justify a small book. But from the system designer’s perspective—using the SoC, not creating it—everything reduces to five key points: cost, density, speed, power, and 2.5D. System designers’ experiences will largely be determined by how chip designers manage the interplay of these five factors.
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Cost is paramount. NVIDIA’s Huang may well have been right: with its greatly increased costs, 20 nm may always be more expensive than 28 nm for the same number of transistors.
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Either with or without finFETs, power presents another issue. The sum of static plus dynamic power is unlikely to be half what it was at 28 nm. But density is going up by a factor of two. Arithmetic says that power density—and hence local heating—will limit both layout and clock frequencies in some 20 nm blocks.
A nice one posted up thread on general issues with smaller process nodes:
But the difficulty inherent in printing ever-finer features has now taken its toll. “When we got to around 28 nm, we were actually pushing the limits of the lithographic tools,” says Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries, the world’s second-biggest chipmaking foundry after Taiwan Semiconductor Manufacturing Co.
To deal with this, Kengeri and his colleagues were forced to adopt a lithographic technique called double patterning. It lets technicians pattern smaller features by splitting a single patterning step into two, relying on a slight offset between the two steps.
Intel used the technique to form transistors on its 22-nm chips, but it stuck to single patterning to make the densest metal layer. Pushing the technique to its limits, the company made wires with a pitch of 80 nm, which encompasses the width of one wire and the space to the next. By adopting double patterning, GlobalFoundries and others could push the pitch down to about 64 nm for their 20-nm chips. But that move came with a significant trade-off: Double-patterned chips take longer to make, adding significantly to the cost.
http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicatedEven Intel (who is generally 12 to 18 months ahead of the pure play foundries) has pushed back their 14nm timetable. This is Intel, the king of chips who can do things other companies can only dream about. Unusual for them they are also splitting the launch. Mobile (where power reduction matters the most) is delayed "only" 1 quarter, desktop (mass production, lower margins, yields more important) is delayed 2 quarters to the second half of 2014.
"It was simply a defect density issue. As we develop these technologies, what you do is you are continually improving the defect densities and those results in the yield, the number of die per wafer that you get out as the products. What happens as you insert a set of fixes in groups, you will put four or five, maybe sometimes six or seven fixes into a process and group it together, and run it through and you expect an improvement rate. Occasionally, as you go through that, the fixes do not deliver all of the improvements. We had one of those. […] We have got back now and added additional fixes, gotten back onto that curve, so we have confidence that the problem is fixed, because we have data that it is fixed," explained Mr. Krzanich.
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Usually Intel launches new central processing units based on new high-performance micro-architecture for desktops, notebooks, workstations and even single-socket servers at the same time. This will not be the case with chips to be made using 14nm manufacturing technology.
Broadwell chips will only land into mobile computers next year, according to Intel’s plans. For desktops, uniprocessor servers and workstations there will be so-called Haswell Refresh microprocessors made using 22nm fabrication process. As a result, the volumes of 14nm products this year may be lower than traditional output using a new node. Intel itself has not officially confirmed lack of plans to introduce Broadwell microprocessors for desktops in 2014. It is believed that Broadwell-based products will now be available in the second half of 2014.
Also note the talk about multiple respins at 22nm because defect management didn't meet projections. Intel owning their own fabs can do multiple respins "cheap" for a foundry customer you are talking $5M a pop plus weeks if not months of delays.
AMD & NVidia have both pushed back GPUs on 20nm into 2015 going instead with another round of chips at 28nm.
TSMC and others are busy developing their own technology akin to Tri-Gates. These are called 3D Fin-FETs. The basic design and physics behind these structures are essentially the same, but Intel trademarked theirs first. The problem here is that we are still at least two years away from an effective implementation of FinFETs on any node from any pure-play foundry. So the GPU guys are looking at a new process node that will effectively shrink the transistors, but may not have the electrical characteristics they were hoping for. TSMC is not planning on opening up their 20 nm HKMG planar based lines until Q1/Q2 2014 with product being delivered in a Q3 timeframe. TSMC is ahead of the bunch so far with actually implementing a 20 nm line.
http://www.pcper.com/reviews/Editorial/Next-Gen-Graphics-and-Process-Migration-20-nm-and-Beyond/20-nm-and-BelowEven the design of a sub 28nm chip isn't easy.
One wrinkle, new with 20nm design, is the need for double patterning. To be fair, double patterning is a useful lithography technique. In fact, it is an essential technique at 20nm. On the other hand, poor color resolution, mask misalignment, and pattern interference problems can easily defeat an SoC whose layout is not double patterning–friendly. Double patterning uses two or three masks to image one layer of a chip on silicon. The exposures from multiple masks overlap to create features that are half the pitch that would otherwise be possible using these wavelengths of light. The patterns of the two masks can be thought of as printing two or three different colors (see Figure 2) that combine to form a single layer.
The semiconductor industry has developed several versions of the double patterning technique. Triple and quadruple patterning techniques are being investigated for 14nm and beyond. The success of all these techniques depends on accurate decomposition of the design layout into the multiple masks, precise mask alignment during lithography imaging, and control of variables such as dosage, focus, etch, and overlay. Chip design teams do not need to know much about the specific lithography variables. But teams do need to know this: you cannot print just any pattern you please using double patterning. Using a method of layout decomposition, multiple masks have to be created and combined in specific ways, and some combinations will not work. As a result, managing double patterning effects cannot be left to the physical signoff tool—as was possible at previous technology nodes—but needs a holistic approach. The entire design flow must take double patterning into account to have optimal layout for manufacturing. Specifically, the implementation tool needs more manufacturing cause-and-effect knowledge, so this tool needs to work closely with the physical design and analysis tools. Simply integrating the signoff tools is not enough. Accurate abstraction technologies must be built into placement and routing to handle early convergence of double patterning issues. Throughout the design flow, this integration for double patterning needs to be tighter than existing integration for dealing with physical design issues.
https://www.cadence.com/downloads/files/20nm_wp.pdfTSMC is only expecting to have taped out a HANDFUL of masks by the end of 2014 at 20nm and doesn't even mention 16nm tapeouts.
TSMC has taped out several 20nm chips and expects to let customers start designing 16nm FinFET chips before the end of the year. By the end of 2014 it expects it will have taped out 25 20nm designs and be far along in work on 30 16nm chips.
Thats right, TSMC is expecting a whole 25 designs to be using 20nm by the END OF 2014. 25 not thousands or hundreds but a staggering twenty five. Think every company in the world which uses Silicon and all the designs they may have, TSMC is expecting two dozen designs to be taped out by the end of the year. That is how small that market is. Not even a word about 16nm tapeout in 2014.
So it isn't just NVidia it is across the industry. Everything is more expensive, more time consuming, and more complex. None of this should be taken as a slight at KNC, they have never claimed a 16nm chip will be available in 2014.
So once again KNC saying "we are working on 20/16nm" doesn't mean "we are going to beat Intel, NVidia, AMD, Samsung, Altera, and other silicon giants to market and be one of a the first companies on the planet to mass produce 16nm chips in 2014". "Working on" =/= "16nm mining in 2014". That is a an assumption made by those outside of KNC. 
