Topic: Just what is a clock buffer anyway? - page 5. (Read 16570 times)

I bet you are simultaneously terrifying and total F'ing awesome to hang out with.

You may have judged by my avatar pic, that that wild sort of guesstimate will be adequate to satisfy me for any number of days whose names end in the letter "y".

I mean seriously you fucking trolls, coming from someone who is the MOST PARANOID PERSON YOU MIGHT EVER MEET, AND ANNOYINGLY SO -- dude above here ^ [Edit: I mean Inaba] has got to be less than willingly losing PRECIOUS SLEEP over even being aware of this forum.
There must have been bleeding-edge tech companies in existench in 1986 or 1992 or so ... ok so imagine that OK:  There were no fucking message boards like this for your INSTANT EGO-GRATIFICATION...  And some of those companies MADE IT... Microsoft.
Idiots!

Give me my god damned ASICS or I will come to KC with a fucking shotgun you fools but THEY KNOW THIS!   That's hyperbole lol worst case scenario i get a refund.

...
But don't trust me; I'm a drug-addicted WEIRDO.
Also, come find me -- I get off on that.
Asshole wastes of life with nothing better to do!
http://youtu.be/yqcbu2ozc50

"Worms keep everything... EVERYTHING... Down."

you never have any data to start with anyways.

I would estimate around the middle or end of January for that order number... but I'm pullin' an Elden here and just guessing without any data to back that up.

DUDE:  Josh, Inaba, whatever the fuck your supplier / demanders dub you:
AM I going to get some actual, usable ASIC devices?  My order# is 8814.  Please give me some sort of random, shoot-from-the-hip ballpark half-assed estimate of a ship date for my two (2) Jalepeno ASIC devices.
I paid some ~20 BTC for this preorder.  (I don't remember the exact amount offhand).  PLEASE convice me not to request a refund.  These threads are starting to scare me, bro.
I'm just trying to play it smart and being honest and am humbly requesting the simplest, most honest truth (even if in the form of personal opinion) regarding these trollatious, FUDalicious allegacusatariums.
I drink Steel Reserve, for crissakes.
Help a brotha out.

OMG... SUCH a juicy retort...
dammit to hell...
I have two Jales on preorder annnndddd...
Blerrrggghhheerarhahahaha
...
......

Wow, you caught a typo and have been playing off of that for months, congratulations!  I like how you just skate over the fact that you quoted a Google link, pointing to a thread where someone else uses the term "fully custom" and on the very same page you are correcting them.  Then you glaze over the fact that the announcement by BFL uses the term correct.  THEN you also gloss over the fact that you swore up and down that there was no possible way BFL was using a full custom design... yet here we are.

Dude, face it, you're full of shit.  You know it, I know it... everyone else knows it.  We'll just keep this thread warm fro the next time you try to "educate" someone with your special brand of BS, so we can demonstrate, once again, you don't know what you're talking about half the time.


Well she-it!  I better stop railing against idiots then... ooops, too late.

"Full-Custom" can mean  F**** all.. anyway.

Since you can take an existing FPGA design and convert it to an ASIC,  you have what can be called Full-custom....(in so far as it's your design and its fully custom)
But that does not mean the design is ANY good compared to off the shelf IP.

Because  off the shelf IP is usually developed SPECIFICALLY for a particular ASIC and as such utilizes the BEST possible options for that ASIC, also IP is usually designed by some of the best designers available, whereas many FPGA designs are poorly implemented at best.....

A simple example:

....
My_Process: PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
....
g <= b*c*d
f <=c*d*e
END IF;
END PROCESS;


Wow it uses absolutely the least amount of  terms (it must be fast!!):
Minimum period: 6.431ns (Maximum Frequency: 155.506MHz)


Example 2
....
My_Process: PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
.....
tmp_b <=b
tmp_e <=e
temp_cd=c*d
g=b*temp_cd
f=temp_cd*e
END IF;
END PROCESS;

Minimum period: 3.901ns (Maximum Frequency: 256.354MHz)

1.WTF!!!
(Thats what experience brings to the table)
MORE terms MORE logic MORE routing and yet it is faster!!!  and that is what good IP can bring to the table... well for V1 anyway

2. Writing for hardware IS NOT the same as programming software.

HC

On the front page of your website.


Dude, take a deep breath.  Your Ignore tag is at #F2F2D8.

Elden, you really need to stop when you're ahead.  If you even bothered to look at the screenshot you posted, you'd have noticed that Blazr used the term "Fully custom" and, in the VERY NEXT POST you corrected him.  So somehow, that's BFL's fault.  Yes... makes perfect sense.  Now, could you please stop making stuff up and talking out your ass?

For reference, it's this thread you are referring to, since you're far too busy to click the links you are citing as evidence about how silly BFL is being: https://bitcointalksearch.org/topic/building-asics-117368


So, since you obviously know what you're talking about (can you sense the sarcasm?), could you point out where BFL has used "fully custom?"  I would trust what Nasser has to say far more than I would trust anything you have to say, since you can't even decipher a message forum correctly.  

Incidentally, this was the first post with regards to BFL's products, as you'll see in the quoted section, it says "full custom" not "fully custom."  But go on, tell me again how we don't know what we're doing, even though you insist that we are not doing a "full custom" or a "fully custom" ASIC, and how we're doing "Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips."  Pretty much everything you've posted about BFL's technology has been... wrong.

I don't care if you switch your avatar or not, we've already demonstrated you don't know what you're talking about, so what the hell!

Best post in thread 

Eh?  Are you trying to tell us that "Fully Custom ASIC" is the correct term?

I think this calls for...

http://googlefight.com/index.php?lang=en_GB&word1=%22Full+Custom%22+ASIC&word2=%22Fully+Custom%22+ASIC

If you can't deal with the facts, go ad hominem...



The thread about BFL is still the third hit, more than a month after I wrote that; see screenshot below taken 29-Nov-2012 at 4:46pm PDT.  The second hit is also BFL-related but was started by somebody else, which still supports my statement that "fully custom" is a BFL-ism.  The butterflylabs.com website has apparently dropped down to #5 since I wrote that.

I'm glad you've started using less ambiguous terminology since then.  However I fear that with the latest post by Nasser that progress might be being undone…  Seriously, it just doesn't add up on several different levels, which is why I'm poking fun at it.  If Nasser posts real, self-consistent, credible details on what went wrong with the first mask set and what the plan for the respin is, I'll gladly switch my avatar back.  But I can't blame you for not wanting to give out that much information.



I've never heard of these Kromek people before (they seem to be more of an imaging company than a chip design company) and the Boeing hit is a typo since it's the only occurrence of "fully custom" anywhere on boeing.com.

You should take Elden's words with a grain of salt.  He's pretty smart, but has a history of just talking out his ass, as evidenced by the fact that he just makes stuff up as he goes along:



Emphasis mine. (Google "Fully Custom ASIC".  14k results, most of them not BFL. The ones that are BFL?  Someone else wrote it. (https://bitcointalksearch.org/topic/bitforce-sc-full-custom-asic-83985))

This (emphasis added).  You don't screw around with the clock tree unless you absolutely have to.

In VLSI design there is the concept of fan-out, which is the the number of gates that a gate has to drive. The larger the load on a gate, the more capacitance slows the rise and fall of the signal edge. You can't just take a clock source and hook it up to a couple hundred points around the chip as the capacitance is such that a minimum sized transistor can't drive it. You can increase the drive capability of the circuit by cascading stages making each stage about 4x larger that the last (see FO4) and by buffering the signal. Just increasing the drive capability of your main clock source isn't always the best answer though, and local clock buffers are often used for different logic blocks. It's basically two inverters in series. They aren't a cure-all though. You still run into skew, where the signal from your clock source arrives later at one part of the chip than another, and jitter, where the period of the clock isn't regular. If they already have a working design "without flaws", they better be damned careful adding clock buffers. Depending on how synchronous the design is, it's not trivial to change a lot in your clocking system without introducing new problems.

OK, those explanations make good sense, and are more or less in line with what I expected.

I imagine that a clock buffer, at one end, receives the signal from a clock source and demodulates it (digitizes it, quantizes it, whatever).  Then, based on its now digital interpretation of the input signal, it creates one or more new signals (maybe it has multiple outputs), which may have different characteristics than the input signal, such as amplitude (voltage), wave shape, and probably a delay (offset) relative to the input signal.

I can see this being does at the board level, but does it make sense also at the chip die level?

next "clock block" soon. I bet on performance increase from 60 to 90Gh (why ? -> bASIC - 72GH)

BFL employee 1 - "Hey, look at this, Tom has 72GH !!!"
BFL employee 2 - "Damn, we need to add more clock block"
BFL employee 1 - "Piece of cake, we have enough clock blocks for the whole year"
BFL employee 2 - " So, time to start operation clock block !!!"
BFL employee 1 - "but what do people will say?"
BFL employee 2 - "Fuck this, we will give them 90GH, so they can will wait a few more months, if this is not enough we will give them 200GH or more"
BFL employee 1 - "and later we will say that the Chinese have failed"
BFL employee 2 - "ok, Check in the calendar Chinese holidays"

This is a clock bluffer.

I believe thats called a clock block.