Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary - page 139. (Read 435369 times)

Ah yes, stoopid me. Was thinking Erupter was Avalon.

Sorry I missed the dimensions but it is 80x90x35 mm
The plan is to make it from 165x35 profile , that is sold in 1m long bars
I can now confirm the final price it's 3.92 Eur ( I missed to add the VAT price from the supplier)
The connector area is cut away . On the projected view you see the radius on the inner edge, that is needed to avoid additional side operation on CNC mill
Do you want me send cad data to be added to github ?

Great idea, you could solder the bug(s) to the outside of a copper water pipe bend - hell some people would call it art!



You could probably run the clock through a piece of coax to keep the noise down.  The power consumption per chip is only a few amps - just use bare 12AWG, more art!

*edit* sorry for polluting this thread.

That looks good. I checked the hole and cutaway positions and they are correct. The width and length seem to be a bit less visually than I'd expect. I'm not sure the fins should go sideways. I guess that would depend on how someone plans to install them. That seems like a lot of machining. Is it easier to cutaway the connector area rather than drill some countersunk holes?

LMFTFY

Try this
http://imageshack.us/photo/my-images/153/fan1.jpg/

I'm not sure what you're doing but it was the same last time. Your image links just go to the imageshack site and not to your intended images.

Personally I call it a 'spider', but I've heard 'dead bug' as well.
I only use it nowadays to make loads for powersupplies. It's always fun to see what a supply does when subjected to a pulsed load. A frequency sweep can reveal some issues in the feedback loop of the supply as well.

Ahah! I always just called that an "Air circuit", or a "rats nest", but I guess it kinda resembles a "dead bug" so the name makes sense.

Personally, I've never looked back since getting a breadboard, for rapid assembly/testing/prototyping. The socket adapters can get kinda pricy, but you only have to buy those once.  

Dead bug style sounds a bit odd for a fairly high frequency digital circuit. Those data connections are pretty slow, but what about the CLK line!?! a 32MHz CMOS signal without a clearly defined trace impedance and/or decent termination sounds a bit... daring.  
Yeah those low voltages are great but high currents that come with them are not as much. Just make sure that your supply wires don't desolder themselves in that deadbug setup.  

One of the first things I noticed about the avalon reference design was the low capacitance next to the chip, and how far the capacitors were removed from the package. To me that could mean several things:
1. The ASIC has a ridiculously high voltage tolerance. (I read it was 110nm, perhaps some process property?)
2. A lot of on-package capacitance, there is some leftover space. The die is about 4*4mm and the package is about 7*7mm. That leaves room for other stuff, not just bond wires. (I'm not in the semiconductor business, correct me if I'm wrong.)
3. Even and constant use. Perhaps with a design like this there is very little variance in power consumption over time. Thus resulting in low capacitance requirements. (could be possible, I have no way to check)


@wrenchmonkey
A dead bug circuit usually doesn't use a PCB. Can be pretty usefull for RF stuff that can suffer from PCB interferrence. Other than that, it's a way to prototype really fast. 
  

Pardon my ignorance, but what is a "dead bug miner"?

Updated heatsink design



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Please coment

Check out the AP6502A - it's what I use on the K1.

Dead bug idea is great why hadn't I thought of that! Should make heatsinking pretty interesting too! I'm imagining a watercooling system made from bent copper pipe with ASIC and voltage regulators attached at random intervals using some thermal adhesive. Would look really cool.

Found a 2a 1.22v switching regulator that takes 5.5 to 36v and is only $3.80 in singles, perfect for this kinda thing.
http://www.futurlec.com/TI/TPS5420D.shtml

I ordered a few extra chips to make some dead bug miners.  No doubt I'll struggle with the 1.2V etc but I've wasted $8 on worse things.

I wouldn't worry too much about the software, there will be a bit of time between sample and production, should be enough to iron out the protocol.  Anything that doesn't need a board re-roll is ok.

Nice project over here. Nice work.
I was just wondering about what still needs to be done on the software end.
So, how dramatic will the changes be to the regular avalon driver in cgminer? I mean, it looks pretty flexible as it is. Users seem to be able to chose how many miners run and how many chips per miner. Assuming cgminer accepts any integer value. (does anyone know for sure?) https://en.bitcoin.it/wiki/Avalon#Cgminer_option
I've seen BkkCoins talk about writing a new communication protocol a few pages back. Seems rather drastic and worrisome. But I'm sure you know what you are doing.
As for the raspberryPi, I've noticed that there is a dedicated miner distro being developed. Could be relevant for this project. Here's a link http://mineforeman.com/minepeon/

As for myself I'm more of a hardware kind of guy. I intend to design and solder some nice boards for hobby purposes  , no intention of selling it though. If the avalon guys release the VHDL source for the FPGA I'll go that route, if not I'll be forced to use a microcontroller like Klondike (and burnin) uses. So I'll be watching this thread. 

No it can't. Different packaging, different pin-outs and a whole world of problems.

Try fitting a ferrari engine into a volkswagen bettle and see what happens if no major rework was done.

Another example, try removing an amd gpu and putting that into a nvidia card.

Another example, try shoving an intel cpu onto an amd motherboard.

ASICMINER are not selling bare chips, so why destroy a BTC2 device when the Avalon chips are ~BTC0.08 each?

I am sure it can be done with k1

Not sure what the point of that would be, the ASICMINER chips are different from the Avalon chips...