Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary - page 140. (Read 435369 times)

Any thoughts about getting a 2BTC USB block erupter and ganking the chip from that for testing?

for the oscilloscope user on the go!

Rigol DS1052E 50MHz seems to be the go-to scope for cost-conscious EEs
There was even a simple hack that turned it into a 100MHz version, likely blocked now.
~$350 8lbs - not too heavy, no?

I've had multi-meters made by this company and they worked fine. They seem to stock UNI-T at some local shops in Bkk so I'll check that out when I'm there in a couple days. They aren't very competitive here so I suspect the price is better on eBay but the shipping may offset that.

First line in the specs:
"The volume exquisite and it is convenient for carrying;" ha ha, so typical.

Cheap Oscilloscope

http://www.ebay.com/itm/UTD2102CEL-100MHZ-Digital-Storage-Oscilloscope-7-LCD-1G-Sa-s-Sampling-Rate-/290672019764

A friend just bought one loves it.

The FPGA in Avalon's design is on a different PCB, I think there's 4 different PCBs in their design: hash unit, hash backplane, power distribution and control (which is where the FPGA is).

That LDO is tied only to the PLL power AVDD. I have the same but used a pin-compatible alternate for that part since they are hard to get. That part has a very high transient response, somewhat higher than my choice, so that is a possible variance. I provide one for each bank of 8 chips.

I've tried to keep the 1.2V supply as wide and short as possible from each buck to chips. This is why the regs are in board middle not edge. Hopefully that will improve 1.2V stability and if lucky improve clockibility.

I used to have two but sold them when I moved here. I won't have one now unless I can find a local to mooch off. I could find one quite cheap on ebay but the shipping is killer on the weight of them. I thought about getting a DSO-230 Nano 4 ch. unit but I'm not certain it's actually very good. I'd need to research some reviews first. It's around $170 on several sites. I have a small logic analyser for data signals, but it would be nice to scope the power for a picture of noise.

Word from zefir was they'd ship end of May, but arrive for him mid-June and re-ship to arrive at devs around end-June. So not really any time soon. I'll have lots of time to work on firmware. Will be mounting 4-5 2W resistors on ASIC pad at some point to simulate power use/heat.

The avalon schematics are very interesting.  Just looking at the PDFs now, especially for the power for the chips.

so right now you have 2x 16A 1.2V synch buck regulators [IR3895] , 8 chips per regulator.  dead on with the 2A per chip maximum spec from Avalon. [They should be the only chips using that 1.2V]  Can program the switching freq from 0.3 - 1.5 MHz

Avalon has on hash_unit_power.pdf -- it is a 2 page schematic in altium but they only exported page 2, not page 1.  really common mistake actually.  I will have to look at the avalon files to see what's on page 1..

I see there

* VCC1V2 is the 1.2V node.  this is used on all the schematics, so its "created" on hash_unit_power.pdf/schdoc but it's the exact same when you see it on hash_chip.pdf/schdoc
* I see the 10 chips on hash_unit.pdf.  not sure what is on page 2 of that though
* The FPGA on Avalon's design also uses the 1.2V plane, and they use the same VCC1V2.  Avalon also has a 1.2V LDO connected to this same net! (RT9166A_CXL) - RT9166A looks to be a 0.58V dropout 0.6A LDO.  Assuming it's the fixed 1.2V version.  I'm somewhat suprised they tied both regulators to the same plane.  But i dont think klondike board uses anything else on 1.2V so would not need this.  but it is a delta between the two designs.
* They use the tps40193 , 1.2V 20A buck synch buck regulator, dead on with the 2A per chip max spec.  0.3MHz switching frequency

I think as long as the decoupling capacitance on the chips and the regulators is the same or better it should be fine.  1.2V plane power caps aren't a place to skimp for cost  

If you think about most high power/current devices, you'll see a shitload of very tiny caps on the bottom of the PCB under the chip, and multi-phase buck converters to provide huge current, both spike current and average currrent.  Of course these chips aren't as bad, but if you think about it this is still up to 16x(2*1.2)=38.4W used by the chips.  it looks like Avalon has 1 0.47uF cap for every ~2 1.2V pins on the chip, so clearly they could have added more if needed but did not have to. 


But I believe this is one of the problems BFL ran into with their PCBs.  that core 1.2V can be a real PITA.  if the current draw is too high and voltage drops or there is too much instability on it the chips may malfunction.  You can declock it, lower current draw, and it works, but this kills performance.

This may very well limit OC'ing, far before heating or power would.

If by any chance you have an oscilloscope it would be very interesting to see what that 1.2V plane looks like when testing, and how it changes when you clock up/down.
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also, any chance you've heard when sample chips might be shipping?

Woo! Progress! Thanks for all of your work Bkk.

It does have a PLL. We're discussing the main input clock to the ASIC which the PLL will use. The hash clock is set by config data shifted in with work start data, and can be adjusted over quite a wide range.

Thanks for the input. I have an IR thermometer due any time now courtesy of Bicknellski.
The heat sink will be attached via 4 bolt holes located between each set of 4 ASICs, so they should have good mechanical contact. I expect to test with springs and with just tight bolts to compare. I'll be testing various pad methods - like blue silicone heat pads, copper pads, and just thermal tape/goop. Once I have some hard measured data I'll report and people can decide what they like best.

My design turns out to be very much like the Avalon. Almost exactly, (I think my exposed pads are bigger), without even seeing under the board before last night, but then there is only limited choices given the constraints. It makes little sense to put 16 small heat sinks under the board as the air gap between pads can only lessen the overall dissipation of heat.

Simple explanation: The mining process does TWO iterations of SHA256 per work unit. The controller does the first round SHA256 (1 time) then passes the value on to the “hashers” for the second iterations of SHA256 (up to 2^32 or 4,294,967,296 times) looking for a golden nonce (in parallel).

It would be done for each work unit sent. It shouldn't take much time as it's just 3 rounds of a bunch of rotates, xors, ands etc. It may be feasible on the PIC even but I haven't looked yet. Since work will be queued I doubt it will slow anything down on either a PC or RasPi or PIC, but the PIC has very limited program memory and much is already used for the USB stack. Will look at that some time later.

Does the pre-calc need to be done for each miner?
Any idea how much time the pre-calc takes on a Raspberry PI?
Have you though about using a more power full PIC so you do the pre-calc on the K16 board?
Thanks.

One thing to look at with testing is the realibility of contact to such a large heatsink

Sharing one common block between all 16 chips, and trying to move the heat between them just with an exposed copper square per chip, no local mechanical force holding the heatsink in contact there.  Could be very tricky

May want to get an IR thermometer (FLIR cameras are great but expensive), measure the temp on the top of each IC to see if they're close.  May not be able to measure the temp on the heatsink itself because the emissivity of aluminum and reflections can fuck everything up, but it's usually good on the black top of a chip package.  If you can measure the heatsink though, see if there's more or less heat at the areas where it should be connected to the QFN pads.  Some may not have good contact.

Can also try making the screws looser, run it for a while to see if heat goes up (from worse thermal contact), make looser, check temp, repeat until it gets too hot.  the chips with bad contact should heat up first or faster.

I just really have not seen this sort of shared heatsink design before..

Going through the files atm (kicad seems to be unable to open them so going to try gEDA for the gerbers) -- may be able to make the exposed copper area for the QFN chips larger?  I'm looking at Avalon's design and not sure why theirs is so small.. or why the thermal paste is fricken everywhere.

edit : oh i see now, Avalon design has ground over basically the entire bottom layer as a plane.  then they have ~24 screws thermally connected and pull the heat from the plane to the heatsink.  not bad

Sorry I've been out of the loop for ~2 weeks.  Is this changing the clock to the ASIC for OC purposes? cost savings?

I thought perhaps the ASIC has a PLL inside to allow you to adjust clock frequency in software

I'm a little doubtful it can be removed but I'll test it. To allow for the possibility I moved the clk enable line to be the same as the PIC clk out pin. That way when I want to test this I can just remove the oscillator and jump the enable pin to the osc clk pin, feeding the PIC clock to the ASIC.

The oscillator is 50ppm and the PIC is undocumented currently, though only requires 3% for it's own input so may not be nearly as stable.

Hooray! Now for some chips! Avalon, if you're reading, we need those developer chips sent out PRONTO! 

Just ordered first batch of 20 - K1 test boards. Yay.

I believe that the spec on the avalon ASIC is 10ps for clock jitter.  that's pretty precise.