Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary - page 160. (Read 435369 times)

Probably but maybe not. I recall a year or two ago someone used one with his Ztex FPGA miner and it output too high a voltage (more than rated) and blew the board. It really depends on the quality and specs.

My recent board changes have added a space for a Phoenix terminal connector behind the PCIe connector so that users who want to hook up other power sources have that option and because it's SMD it means that you can avoid any thru-hole solder connections that may contact the heat sink. I tried to place a barrel jack there but they were just too big to fit between PCIe and board edge and still maintain compatibility with right-angle PCIe connections.

You could probably just use a 12v laptop charger they're normally very consistent voltage wise and around the right amperage range for a board or two. Would I be correct in this?

My PSU has two power rails and the second one is already heavily used. Guess I'll have to buy another PSU to be sure that my computer is stable, It's not a big deal if I buy used one or make one myself.

http://extreme.outervision.com/psucalculatorlite.jsp


Input the numbers and let us know if you can run one board. Just add ~32W total to your total and see if you are under your 600W with some to spare. Do you have any Avalon chips?

Would I be able to use one OCZ ModXStream 600W psu both for one Klondlike and my gaming PC(with or without OC)?
Intel i5 2500k 4.2GHz @ 1.25v
GIGABYTE GTX 670 OC - currently at stock but I'd like to able to OC it
Asrock P67 Pro3
Xonar D1
and Seagate 7200 1TB HDD

At this time I believe it reports only found nonces and the chances of collision are slim. I'm basing this off how Icarus worked. Looking at the driver it's likely it also reports back the full midstate and data, which I can ignore since I have that in RAM already. If the driver was smart it wouldn't need that info back either. ie. it stores that info for each known miner module. I think we have to assume this since Avalon has all 10 ASIC chips wired this way. They all connect to a 470 ohm resistor tied high and a buffer to go off board to the FPGA. If the ASIC is "smart" it can detect traffic by watching before using the bus, but I don't know if it does that. It doesn't seem very efficient either to send the midstate and data all back again but if the FPGA cannot store it for each module then it would have to since the Avalon driver expects to read it back.

Are you assuming only one chip will report data at a time (i.e. data is never being sent concurrently by more than one chip)? I have a feeling all chips will report some kind of status not just when a good nounce was found. But I guess we won't know for sure until the communication protocol is released.

Yes, to the same extent, as I use the chips in exactly the same way. This wouldn't happen if the hash engine was damaged but would if the data path from input to bypass output was broken somehow.

edit: Note that technically it would only lose those after the dead chip in the chain, so some random number from 1 to N.

The chips are supposedly 100% tested at the factory. I think TSMC is trustworthy that way, seeing as how they're a huge tech company supplying most of the worlds other huge tech companies. Presumably a board assembler would also detect this during testing.

OTOH, doing DIY reflow at home is more likely to experience problems as getting the reflow profile perfected to assure consistent results may be more than most can manage.

Sorry I haven't followed Avalon's design closely. Could you clarify that Avalon would also lose all 10 chips in a bank if any one of them failed or was damaged?

It's a wired OR bus, all outputs join together into one PIC input. The PIC does have a UART and amazingly I just hooked REPORT_P to that pin. What's even better is it has IOC (interrupt on change) so I don't have to poll it.

Just like the Avalon, the Klondike will work with how the ASIC was designed to be used. Instead of 10 chips/bank I'll have 8. For partial fills I haven't decided yet what I'll do - either I'll have to divide the range by N chips, or I'll just ignore that and divide by the next higher binary multiple, but only shift N sets of data. While it won't check every single hash in the range the probability of finding one doesn't change. You just have a lower hash rate due to less chips.

same thing
tell me when this is ready

I hope there is a mistake in what you have said, because it scares me a lot. We don't know what the yields are on Avalon chips, and I would seriously prefer a solution where only the damaged ASIC is the one that does not function. Losing a bank of 8 is significant, imho.

Also, what happens if a bank is not full, e.g. 6 chips instead of 8? I imagine there are plenty of people who don't who's total number of chips don't divide nicely by 8, and if we are shipped untested chips then yields could make that worse.

It looks like the hash chip sends back the report data asynchronously. Is a PIC controller capable of concurrently clocking in results from multiple chips?

Thank You, Bicknellski and steamboat.

Updated Github.

Added new items to parts list for LEDs, Thermistor, resistors and ASIC VDD ref. supply.
Changed capacitors to match Avalon specs and quantity. May have to adj. again soon.

Added incomplete Gerbers to k16/plots directory. These are Gerbers for the real board but expect changes as I know at least a few items missing and a few I'll be moving. The drill file is there so  you can use that to locate accurate position info, which may change so don't treat as final. And the layers are there - but incomplete as I've hardly done any data signal tracks on the inner layers, and power supply still needs several changes. But this gives people some pretty pix to look at in better details than 3D renders.

Enjoy.

Nice one steamboat +1. Thanks from all of us!

Oooh getting so excited. Wish I could help more.

I am going to see if I can get some of those VGA style heat sinks aluminum extruded to you BKKcoins. Just need to track down a few of the manufacturers here in Indonesia. Maybe another aliexpress shipment from China headed your way if I can swing it.

BkkCoins is scheduled to get sample chips from batch 1 from my purchase.

+1  I think anyone with a larger order of chips should see if they can shunt the "test" chips BKKcoins way if at all possible. I am trying to determine what if any Avalon test chips I might be getting from the group buy. That would be a priority I think as the sooner he gets the testing chips even if he is not ready for it the better.

I'd like to add... if there's anything you need, please let us know! I'm sure it's the least we can do for the time you're putting in.

The K64 is just 4x K16s on one board so the two can interconnect as if the same. For now I'm considering the limit on chaining the boards to be 8 K16 boards. I think that's a dependable number. However, it could easily be more as some people report having 25x I2C LED boards on an bus. I'll do testing when some are built. Regardless, at some point I'll put together a tiny I2C boost jumper that slips over the pins joining boards and expands this number. Also, initially I'll stick with 8-bit addressing and on I2C I think this means just a bit under 128 boards could be chained in theory, off a single USB connection. I doubt anyone will do that, and it probably makes more sense to run about 16 boards off a USB, and then use a USB hub to expand further, seeing as how they are dirt cheap and let you use the higher bandwidth of USB vs. I2C.


The result data gets back from the ASIC to the PIC via a secondary route as serial data. It is only a 4 byte nonce (I believe), and so is a very small amount to return back to the USB host.

I don't want to even talk about selling boards until I have a working prototype but everyone keeps asking so we have a lot of discussion about sales - that day will come and deals will be made. I will try to do what I can to get boards into assemblers hands so that miners can just buy boards and hook'em up.

I'll try to put a drill file on github (but design could change if there is a better way to do it).

There is 4 corner holes and 4 spaced between the ASICs with the intention that the heat sink can be clamped down above each set of 4 ASICs. I think probably the 4 between ASICs are better suited for attaching the heat sink, and the corner ones for stacking with spacers or bolting to a case. But it could work out that bolting down the heat sink at the corners is feasible too. If the fins are cut back a bit there then spacers could be mounted on together with heat sink.

When I have a prototype I'll attach some test heat sinks and see what works best, and test with the new IR thermometer gun that some kind member here bought me.

BTW I'd welcome any sample/test heat sinks users want to send me so I can try them out and measure temperature with different air flows, etc.

Heatsinks?

I know you are still reworking the board for more important aspects but have you given more thought to the attachment of the heatsink Bkkcoins? Will we more likely to be bolting a single Aluminum heat sink to the back of the board? Where will the through holes be?