Chaining: The I2C protocol have a 128 devices limit. The chain connection will be between Pics? or 1 pic will controll all asic chips? (this limit to 8 boards per PIC connect to the host)
Well, in theory 1024
boards should be doable and later on I'll make a PIC "hub" that can extend the bus. One PIC controls it's 16 chips. It gets work from the I2C bus and sends results back that way. The USB connected PIC will pass info to the I2C bus and control it's own 16 chips. The real limit is the bus capacitance and I'd say 8 boards is probably doable if they are not far apart. Some users with LED units report they run 25 boards at 14" intervals without problems but I wouldn't count on that being true until tests have been run.
The PIC will connect to usb bus? Have you consider the RJ45 circuit of your old FPGA design?
I was going to originally do Ethernet only but reading thru the cgminer code made me realize that some hashing would need to be done in the miner code. I didn't want to get into that stuff on the PIC (rewwrite the entire miner code) so I back tracked and decided to keep the PIC code simple and have it just co-ordinate work.
The fan control circuit will be integrated? or will be an external module? (if it`s integrated the pic can shutdown the miner if overheating, if it`s external we can replace it with a homebrew cooling system).
The fan control is handled by the PIC on each board. There may be an API to get/set status/control values from cgminer. It will be optional and since the firmware will be open source you will be able to modify it to work with something other than a plain old 3-pin fan.
About asic chip failure debug: maybe 4 leds for show the number of damaged chip?
I'm not going to put LEDs on board, except maybe for power ON status. I'm assuming that the USB will work and that any status/debugging info can be shown easily on the user interface, or be queried via an API with console commands. The cgminer driver should also allow for debug info to be logged as I'll likely need that anyway.
BkkCoins
I also have a couple of questions.
Will the work be divided between the group of 16 chips Each chip does 1/16 range of nonce?
What if Avalon chip can't divide the work this way?
That is the way the Avalon works now judging from reading the cgminer driver. If for some reason I'm wrong about this then the PIC will be smart enough to send the ASIC the correct data. Currently the cgminer driver calculates the range based on chips per board and sends a start value for each chip shifted out serially. But I expect to change this so the cgminer driver sends the master nonce once for each board and the PIC masks the upper 4 bits and shifts it into the ASIC chain. This should be less work for cgminer and only minor changes in the current driver. We'll see.