Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary - page 79. (Read 435369 times)

GREAT NEWS!

I've got it running at 300MHz and it's much more reliable than at lower speeds. I now have 2 chips doing 600 MH/s total with fairly long periods with zero HW errors.

I tried several capacitor values for result capture and the 30pF works well up to about 360MHz. At 380MHz it's lost sync. I tried a brief run at 360 MHz and it worked ok. I need to get a fan working before I run extended tests at higher clocks.

I had to fiddle a lot with the work unit cycle timing. Seems I don't know what's going on because calculated times weren't right. By trial and error I adjusted it to get very few duplicates. I've also implemented code to only update clock cfg when it changes, not every work unit. But I haven't altered the result capture code yet - so even with no extra schmitt buffers and slow result code it's actually doing ok. At 300 MHz the result data comes out at 2.35 MHz.

Here's a pic of the result data at 300 MHz:



I'm just letting it run for a while at 300 to see how it holds up. Chips and heat sink get fairly hot to touch but I have just convection cooling for now. According to IR thermometer the heat sink is about 54C and the chip may be about 63C.

Good catch on the K1 errors there villex on Today at 01:31:41, got a BTC address? We should be giving a little "TIP" to people who find mistakes in the BOM like this.

Keep up the effort BKKCoins we are hanging on every drip of sweat!

Yeah, the 'good ole' lead based solder is really amazing, especially compared to the RoHS solutions.. ugh.

they actually have pretty strict requirements 'by the book' for solder paste.  Stuff like "use within 6 months of purchase, keep refrigerated, use (reflow) it within 4 hours of application", but Sn63Pb37 is probably the most robust of all

Yes. It's just el cheapo "Mechanic" paste. I can buy it in the "phone" market in Bkk for about $3 / 50g. That's a wholesale market full of mobile phone parts (chips, LCDs, and everything else inside phones including main boards readily available) and many little stalls that do rework repairs on phones. I have a few jars but I opened the oldest first and tried that. Amazingly, it had been sitting here in >30C heat for 16 months and who knows how long in Bkk before that. And then once I stencilled it dried out over about 6 hours before I reflowed it. But it worked fine, at least so far it's working.

When I tested the oven I ran it up to around 220C to see how long it would take to reach that. It was quite close to the "typical" reflow profile and just by having the door a bit open or turning the power knob on/off a couple times I could hold it back for the soak time. It was totally awesome when I had the board in there and the paste all turned silver right at the time it should, and a real relief.

Yeah there is a learning curve with reflow / solder paste / solder stencil / etc.  I assume you were using Sn63PB37 solder?  That will have the lowest temp to reflow

It can be really tedious handplacing all the parts as well, and it has to be done within the working life of the paste

One thing that might be useful is to use the iron to apply heat directly to the pad on the opposite side of the asic, through the thermal vias.  this would reflow the thermal pad, but not the QFN pads

Most of the board except ASICs was done using stencil, hand place parts, toaster oven. The stencil was cut on my Silhouette SD. The toaster oven is a cheap 800W one worth about $25. I did a couple timing runs first with an empty board, my IR thermometer and a stopwatch, but I have no controller, so just measured temp and timed.

For the ASICs I used a toothpick to dab paste on the pads (well, more like along the pads in a line),  then placed the chip with tweezers, and then used a rework hot air gun to heat. First time I had a capacitor next to ASIC go tombstone again. So I got some kaplon tape and this time I placed little bits covering the other parts near by. I heat gently from about 10cm for 30 secs. Then I come in closer and heat the chip until the paste goes silver, and back off to 10-15cm for short time and then let it cool down.

So far I haven't done too badly but this isn't my forte really. I don't do it often so every time is a bit nerve wrecking as I worry about frying them. I think I've placed a bit too much paste each time so will cut back on the next one.

Not sure which previous statement. I only meant I'm getting double rate because now I have two chips installed. Same clock as before, but also better HW error rates now, though every now and then it blows a gasket and chunk of them pop up. I've been doing some testing with sending work data with clock cfg disabled but I'm not sure it helps. My theory was that every time I send data I'm sending clock cfg, so maybe that causes the PLL to re-lock. There is a bit that says "no chg clock this time", but I was distracted by other errors. Once I get further I'll try that again as maybe it will let the PLL stabilize more if not being updated with new cfg.

I have had it run at 220 MHz but it's not stable due to result capture timing I believe. It's actually saying about 330 MH/s when I run at 128 MHz, which is a bit high.

Also, I have a RasPi set up now and have been running the Erupter on that (off a hub). I'm just testing the Klondike there but seems like something is fishy. It worked earlier but I had a bunch of changes to pull over and it got muddled up. I expect I'll have that going soon.

Currently he can only clock each the ASIC at 180MHZ  its double the previously stated rate because there are 2 chips installed now.

Congrats on your progress BKK!

Regarding the previous statement, are you getting double the stated 333MH/s per chip or your getting double the rate that you had previously stated?

That's weird. 6.8nF is correct and the Murata part# for 6.8nF is obsolete. So I've changed it to a Vishay VJ0603Y682KXXCW1BC instead. While checking that I noticed that the other 6.8nF in the schematic should be 10nF. I can't see any reason why I would have changed it to 6.8. So I've fixed that as well and to consolidate it with the 0.01uF on the oscillator I changed that one to 0603 instead of 0402 - so that double qty can be ordered of same part.

ERJ-3EKF2201V should definitely be ERJ-3EKF1001V - that was changed some time back and the part# didn't get changed with it. Thanks for finding these and pointing them out.

But also, two of those could end up being 470R instead of 1K. I'm still working on the result capture and it turns out that the result data rate is actually tied to the hash clock (apparently hashclk/128), which is idiotic IMO. So at higher clocks the pullup resistors may actually need to be 470R, and the capacitor lowered as well. Although when I tested 500R before it made little visible difference to rise time.

I'm was just pushing to higher clocks and couldn't figure out why it wasn't working until I scoped the result data again and saw that the bits are getting shorter, so much so that the delay circuit delays too much and the data never drops to "0". Geez. This also means rewriting the UART code to handle the nonce bytes more quickly by moving completion outside the ISR. I'm in the process of fixing this now.

BTW I did get a second ASIC mounted and have been battling with the stuff above. At first it had issues with 1.2V power shorting under the chip (hidden solder bridge), and after I reheated and bumped the chip a bit it cleared up. The nice thing is that I can say now that a short on the 1.2V doesn't blow anything or cause issues with the buck reg. It just shuts off without any drama. I had some issues with nonce range duplication due to testing on one bank when the code was written for interleaved banks - once I realized what was going on it was easy to adjust.

So it's running on both ASICs now and getting double the rate but I still can't go above about 180MHz until I change the result delay capacitor, which I don't want to do now at night. So tomorrow will get that switched out and see a faster capture signal. That should allow boosting the clock. The board is now mounted with thermal compound on a beautiful black heat sink sent to me for testing by steamboat. The chips are barely warm now.

Because the ability to get 30-50% more performance out of the chip is not relevant to design..? 

Hello, I'm seeing in the K1 part list the GRM188R71E683KA01J marked capacitance as 6.8nF but in the datasheet is 68nF. Which one is needed?
Also the ERJ-3EKF2201V is marked as 1K Ohms and in the datasheet is 2.2K

So no talk of cooling in this thead only board design? Got it 

How about you move all this waterblock crap to another thread so we can stay on the topic of board design here?

I designed a water block that two k16s would bolt onto back to back. The waterblock is two pieces that fit back to back and are bolted or tig welded together. I had planned on using 13 of these "sandwiches" in a rack. The block is designed based off some gpu blocks I have. I sent out for a quote just waiting to hear back I think in large quantities these could be fairly cheap. I posted about this in the bitburner thread earlier when someone posted a similar concept. I've had the design finished for over a week. I just used some of my 3dprinting software to design it. Too bad my printer wont print aluminium.   

Yeah so looking over cooling options, it seems the most efficient would be, if possible, sandwich waterblock between Klondike boards, ideally between two K64's, to minimize # of blocks required.  But the heat from 128 chips to a common block might be too high.  Might be better to do K16x2 or K64x1

I'm sure you could find a balance point between the two. Switching frequency can go well into the Mhz range, the regulator I've speced can operate 3 phases up to 2.1Mhz 120* apart, which would enable a very small value inductor and reduced size decoupling caps. However the higher you go up in the Mhz the higher the EMI is and you then your into the RF voodoo with curved traces and shielded signals. Everything in circuit design is a trade off. It's all about trying to find the balance that fits your application.

You may have to make tradeoffs for efficiency vs overclockability as well (i.e. switching frequency).  It's currently at 600khz (300 - 1500 khz is the range of possibilities).

Likewise i think the power inductor (0.36uH, <1.8mΩ) also leans more towards efficiency than ripple current

this might be more complicated though.. trading transient response for voltage stability and (lack of) noise

Consider this the current design has 3 buck regulators and 2 ldo regulator add the losses up on those and then multiply that by how many boards most of us plan to use. I personally plan in the end to run 5 racks of 26 boards that would be 3.7 KW at say 20% is around 750w (540kw per month 24x7). If it could be brought down to around 10% thats 400w (280kw per month)  or 5% less than 200w (140kw per month). these percentages are just theoretical but show the cost saving over time. Also consider the cost of one chip vs 3. A 3 phase chip running in 2+1 would reduce component drastically you could generate the 1.2v rail an 3.3 with one chip. One polyphase chip is about $6 in single quantity with the ones use its about 3~4 per chip. Not to mention you could reduce the component sizes as well. Power cost, Production cost, and hash speed could all be improved with the regulator design.