Believe me, if I had access to 400k$ I would get one built. But I don't and so have work for a living like everyone else.
I know of at least two groups that are actually doing this on 20nm technology at the moment, and they aren't planning on selling their product to the masses. Frightening thought.
As for Mr. Dadda, I suspect that because of his abilities and reputation he's paid extremely well and has other interests. Read some of his papers, you'll find it a worthwhile exercise, he's a very clever man.
Topic: KNCMiner and their 'magic' SHA256 alogorithm - page 6. (Read 8790 times)
Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic.
so where is Dadda's miner if he so supa??
Ya where is your supper miner, seems like you know everything about Asics ...
Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic.
so where is Dadda's miner if he so supa??
perhaps, when they say they are "improving the Algorithm" they are refering to their implimentation of it. Perhaps their implimentation had issues and they improved them.
I am not an expert and can not pretend to be. But I think there are revolution ways to break the balance of ACIS design.
Maybe the details of KNCminer ACIS design is not convenient to disclose.
So No news is good news.
Just waiting three months to see the result.
So many thanks to your deeply explanation of different ACIS design.
Maybe the details of KNCminer ACIS design is not convenient to disclose.
So No news is good news.
Just waiting three months to see the result.
So many thanks to your deeply explanation of different ACIS design.
Good that you designed asics. Well in prior publications (prior to 2011) I haven't seen that such balancing was well covered. There's really MANY solutions like that, basically I have explored likely most if not all of them. These have different implications depending on underlying cell implementation... But - is it really something that would be published ? For me it seemed like good r&d job that anyone who would like to produce optimized algorithm should pass. And it was surprising that many developers actually ignored such optimizations. I remember that I got to them much much earlier than say I understood underlying low-level structure of spartan fpga. So not looks like something impossible complex. Especially for those who pretend to be experts.
Glad to see some of you have actually started to think. I have actually designed asics before, and am well aware of what is real and what is not in device specifications and performance. I would advise anyone with an interest in the asic implementation of SHA256 to read some of the academic prior art available as I have done. Then let's hear your thoughts.
I have no alligience to any of the asic companies, but I hate misuse of data and bad 'technospeak'. I also think any company that wants your money should answer your questions without you having to ask them. If you think differently, then you're an idiot.
As for BFL, they dug themselves into a hole and did'nt try to get out. They need a good PR man to repair their tattered reputation,and to do something to restore the faith in their customers.
Problem is here, you all want to be rich - nothing wrong in that - but don't make the mistake of financing your future competition.
I have no alligience to any of the asic companies, but I hate misuse of data and bad 'technospeak'. I also think any company that wants your money should answer your questions without you having to ask them. If you think differently, then you're an idiot.
As for BFL, they dug themselves into a hole and did'nt try to get out. They need a good PR man to repair their tattered reputation,and to do something to restore the faith in their customers.
Problem is here, you all want to be rich - nothing wrong in that - but don't make the mistake of financing your future competition.
So to any of you that are prepared to swallow the shite that KNC put out: Beware.
I'm not saying they are scammers, but they are dishonest with their information, to put it mildly.
I'm not saying they are scammers, but they are dishonest with their information, to put it mildly.
While you may be right in saying this is the "magic" behind KnC:s algo, the way you express your thoughts reminds me of another forum dweller here...
Is that you, Josh?
What magic? What algo?
There's no KnC ASIC yet. It's just a promise. All this is just mental masturbation.
"An ASIC Design for a High Speed Implementation of the Hash Function SHA256 (384, 512)", Dadda, Machetti, Owen (2004)
I don't know what the precise language is which you're taking to task. But if KNC or OrSoC's guys found, studied, and implemented this or another implementation scheme for SHA256, then it's semantics you're arguing. What I mean is this: there is only one exact square root that maps uniquely on a real number. But if it mattered, and you had a way to make a value converge to full float accuracy faster than mine, could I take you to task if you said you had a better square root algorithm than I did, if we both got the same correct value?
And, no, I don't have a KNC box on order. I don't have any hardware on order. The mining ship has sailed for anybody that doesn't have their own unlimited supply of chips and the facility to build the boards.
Well. That 36% speedup is likely "old" trick of balancing delay between EFGH and ABCD pipelines... I consider this as an old trick that everybody knows now :-) So nothing new and unusual.... I think today this is public domain and well-understood technique at least of those who deal with miners :-) Avalon has it for example.
Very important feature. There exists several ways to balance depending on performance of underlying cells, but idea is the same. BFL by the way seems not to implement it in their FPGA products that I suspected about 1.5 years ago when tried to benchmark my code with quartus estimations. There can be actually some invariant transformations of pipeline that however produce different timing balance. Best of course when you get equal delays.
Look carefully code below, it is what I actually use in last design. You should see extra subtraction for example. It may seem like unnecessary operation, but it helps to balance delays and get overall better performance. Trick like that existed already in my earliest bitstreams in end of 2011
So now there's more tricks but they are not related with logic models, but layout issues.
To sum up - if they claim they use such balancing - means that they worked really well and aware of details, unlike BFL did, good sign. I think they could disclose now more :-)))
Very important feature. There exists several ways to balance depending on performance of underlying cells, but idea is the same. BFL by the way seems not to implement it in their FPGA products that I suspected about 1.5 years ago when tried to benchmark my code with quartus estimations. There can be actually some invariant transformations of pipeline that however produce different timing balance. Best of course when you get equal delays.
Look carefully code below, it is what I actually use in last design. You should see extra subtraction for example. It may seem like unnecessary operation, but it helps to balance delays and get overall better performance. Trick like that existed already in my earliest bitstreams in end of 2011
So now there's more tricks but they are not related with logic models, but layout issues.To sum up - if they claim they use such balancing - means that they worked really well and aware of details, unlike BFL did, good sign. I think they could disclose now more :-)))
Code:
always @(posedge clk) begin
/* Compute round expander values */
w0 <= w1; w1 <= w2; w2 <= w3; w3 <= w4; w4 <= w5; w5 <= w6; w6 <= w7; w7 <= w8; w8 <= w9; w9 <= w10; w10 <= w11; w11 <= w12; w12 <= w13; w13 <= w14; w14 <= w15;
if (s[0]) w15 <= `REV(win); else w15 <= w0 + `S0(w1) + w9 + `S1(w14);
/* Compute HGFE */
hr <= gr; gr <= fr; fr <= er;
if (s[2]) er <= `REV(el); else er <= `E1(er) + `CH(er, fr, gr) + agwk;
/* Compute ABCD */
dr <= cr; cr <= br; br <= ar;
if (s[4]) ar <= `REV(al); else ar <= `E0(ar) + `MAJ(ar, br, cr) + ds;
/* PREPARE */
kr <= `REV(k);
ds <= er - cr;
agwk <= w15 + ar + gr + kr;
end
I am really not interested in Open Days, just plain old transparency. It works.
Got one on order, have you?
Got one on order, have you?
Open days is all about transparency.... Yes i got an order, KNCminer has been cool from day 1.
i dont know, but i think troll..
No, this is'nt Josh, just a concerned citizen. I doubt that Josh has the time or inclination to worry about what KNC may or may not claim at present. In all fairness to him and BFL, they've never put out any technical misinformation about their products.
Err... here's a partial list of lies/omissions/misinformations about BFL products:
- chip power estimates
- chip production details
- estimated hashing power
- PCB specs
- all kinds of part delivery dates
- product specification changes
- production capacity
- shipping schedule
While not everything on that list is strictly technical, it does illustrate how anything that comes out of BFL "PR" machine should be viewed with suspicion. Anyone care to add more?
No, this is'nt Josh, just a concerned citizen. In all fairness to him and BFL, they've never put out any technical misinformation about their products.
hoooboooy that's Josh right there
I am really not interested in Open Days, just plain old transparency. It works.
Got one on order, have you?
Got one on order, have you?
Date Registered: June 02, 2013, 10:19:42 PM OK!
Yep, pretty transparent attack on KNC. Notice how he has not addressed any rebuttals to his statements.
I am really not interested in Open Days, just plain old transparency. It works.
Got one on order, have you?
Got one on order, have you?
Date Registered: June 02, 2013, 10:19:42 PM OK!
In addition to the previous arguments:
In an ASIC/FPGA it's not really only an algorithm, so another aspect comes into this: Creating a sufficiently optimal representation of the desired logic in VHDL/Verilog that lends itself well to chip layout / signal paths etc. -> This is what will allow you to either pack more parallelism into the chip real estate OR (tradeoff) utilize higher clocking. Layout and routing on the chip is nontrivial and using only the auto-functions of the design software might not give optimal results. If you are in a hurry to get a working chip in volume production, that's ok, but if you spend some more time on this, you might gain 15% or even much more in terms of attainable clock speed
Being able to clock 15% higher due to refinements in your chip design is a good thing, neh, if you can do it?
In an ASIC/FPGA it's not really only an algorithm, so another aspect comes into this: Creating a sufficiently optimal representation of the desired logic in VHDL/Verilog that lends itself well to chip layout / signal paths etc. -> This is what will allow you to either pack more parallelism into the chip real estate OR (tradeoff) utilize higher clocking. Layout and routing on the chip is nontrivial and using only the auto-functions of the design software might not give optimal results. If you are in a hurry to get a working chip in volume production, that's ok, but if you spend some more time on this, you might gain 15% or even much more in terms of attainable clock speed
Being able to clock 15% higher due to refinements in your chip design is a good thing, neh, if you can do it?
I am really not interested in Open Days, just plain old transparency. It works.
Got one on order, have you?
Got one on order, have you?
And speaking of said, here are some questions you shouldask anyone wanting your money up front for any asic product:
1. Who is the silicon foundry?
2. Are you using a Multi Project Wafer service or a full mask set?
3. What is the chip size?
4. How many pipelines does it have and what is the operating frequency?
5. What is the target package type?
6. If you are using a full mask set ($1.6 - $2.3 Million for 28nm) who or how are you financing it and what are your contingency plans if you need a respin?
7. To get '90 day' production you need a lot of chips, meaning you need several wafers (costing 15 - 30k dollars each in a small geometry). Refer to 6 above.
8. What software tools have you used for development and if they are commercial ones like Cadence, exactly how have you financed them up to now?
9. What happens to my money/order if you miss the 90 day target?
10. Will you publish an order backlog summary for purchasers to examine?
11. Will you publish the invoice for NRE for purchasers to see? (ie to see that it really is x nm)
Feel free to add your own. There is absolutely no reason for any company wanting your money NOT to answer these questions.
There has been 2 open days at KNCminer. They answered pretty much all the questions asked to them. You could have sendt your questions with someone attending.
The real question to ask yourself is:
What do I think an improvement of x% to the SHA256 algorithm means?
Most everybody will think it means x% more hash rate, yes? Inferring that their SHA is better than others,
yes? So their product is superior?
You cannot change the SHA256 algorithm or it isn't SHA256 anymore. A hardware tweak which enables a higher clock rate has nothing to do with the algorithm itself, so why try to claim otherwise? I don't even know if KNC have used the methods in the paper - I doubt it - and they have given no details about their mathematical wizardry. I would, if I was them, there is no shame in being genuinely creative, like the
authors of the paper. But to use these tactics?
What do I think an improvement of x% to the SHA256 algorithm means?
Most everybody will think it means x% more hash rate, yes? Inferring that their SHA is better than others,
yes? So their product is superior?
You cannot change the SHA256 algorithm or it isn't SHA256 anymore. A hardware tweak which enables a higher clock rate has nothing to do with the algorithm itself, so why try to claim otherwise? I don't even know if KNC have used the methods in the paper - I doubt it - and they have given no details about their mathematical wizardry. I would, if I was them, there is no shame in being genuinely creative, like the
authors of the paper. But to use these tactics?
I am sure KNC was talking about improvement to the Bitcoin hash algorithm as it pertains to mining not changing or breaking SHA-256. Improving the Bitcoin mining algorithm is possible, since you do not need to produce all 256 bits of the second SHA-256 hash. You only need to produce the part that is examined for difficulty. The ZTEX FPGA mining code has an example of this.
Also, they are talking about the algorithm as instantiated in silicon, not the SHA 256 pseudo-code algorithm. How many registers are used, how the adders are built and shared, how many loops are performed. There are endless possibilities for improving how SHA-256 is done in any language be it C, C++, Go, Verilog, or laid out in an ASIC.
No, this is'nt Josh, just a concerned citizen. I doubt that Josh has the time or inclination to worry about what KNC may or may not claim at present. In all fairness to him and BFL, they've never put out any technical misinformation about their products.
Jump to: