Topic: Looking for system integrators for new asic - page 3. (Read 21956 times)

Count me in as very interested in this!!!!

holly $#!+
one chip pulling 60-120ghs and 15W?!? That is way better than I had guessed. I was going for 64 cores, but not that frequency or that low a power consumption.

Cooling requirements should be tiny too. Just a small 1" square heat sink and fan would more than do for a high speed/power version. And the boards will be tiny with the SD slots and OI taking up most the realestate.

Thanks for the info Helveticoin. I'll be in the market for some mining equipment in a couple of months, now I know what I'm saving for (just need a price!)

Getting 60GH/s with 5Watt is a very good result ! :-)

No, it does a double hash.


You are incorrectly assuming the production wafers would contain only a small number of bitcoin asics. They will contain only bitcoin chips, using the same mask, but shielding everything we dont need.

Our first partner has had a working prototype for almost as long as we have. The second prospective partner only has documentation atm, we have not signed with them yet.

And yes, one dual iterated hash per clock.

Of course, otherwise your future customers will spend all their money on Avalon now :-)
Assuming SHA256 engine computes a single sha256 function You would get 30-60GH/s and use 5-15W for this. This is a little bit worse than our estimations for standard ST CMOS and the rolled design. So I assume You did not use any of the new processes advertised by ST (FDSOI / body bias). But still getting the clock tree right for such a big structure is a nice achievement :-)
I still don't understand Your statement about the high chip costs. You don't want to create a real mask set for the chip and continue with the MLM-MPW mask? I don't think this is a good strategy. By the time the chips enter the market the price per chip will be probably in the order of $2 per GH/s => $60-120 for Your chips. If You get only few chips per wafer this price would be too low. I would invest in a full mask especially since these chips will survive on the market much longer than the competing chips.

Couple questions, if you will.
Does each engine produce one Bitcoin double SHA2 hash per clock cycle?

Also, have any of your first round partners met with you in person and seen a live demonstration of your hardware?

@everyone sending forum messages and emails;
I apologize for not answering each and every one, we do read them all and we will contact most of you when the time is right.  We've made a few very good contacts and we will concentrate on those first, to make sure we are not wasting your and our time. We do not want anyone else to commit time or resources before we have finished our incorporation and signed a deal with the fab and some IP owners.

@Phinnaeus Gage
We are quite aware of our actual competition (Butterflylabs, Avalon,..) , but we are unfamiliar with the companies behind some other recent announcements that are suspected hoaxes. Many people asked us if we had any relation with them, I just wanted to make clear that we do not know them and they are not using our chips.

@tytus
The answer is your number 2. It is both a MLM and MPW, the mask containing several test structures and designs for customers and our bitcoin miner. Because of this, we only had a relatively small number of candidates to begin with, and since this node was/is experimental, our yields, especially on the first wafers were much, much lower than usual. Only the last few wafers yielded reasonably and as a result we have on the order of a dozen functional chips.

@Magnate
We will come out with a press release once all legal hurdles are taken and the deals are inked. I cant give a precise date for that, I do hope its within the next few weeks.

As for the performance estimates; we wanted to remain tight lipped about this to not steal our partners thunder, but since they actually press us to get some more info out, I will give you some. Our design contains 64 SHA256 engines (at least 60 are expected to be operational in each chip). Maximum clock frequency of our samples, depending on voltage, ranges between 1 and >2 GHz. Power consumption per chip is in the 5-15W range.

When should we expect the official release with the integrators?

The "USB-ASIC" thread shows a cool idea. Single chip on a tiny PCB USB board. A 28nm chips could get maybe 8ghs compared to BFLs 4.5. Maybe more with a small heat sink and a decent hub with good current flow

Summer 2013... my guess.

+2

this project certainly seems more reputable than the rest of the recent offerings. Helveticoin seems to actually have a clue and a business plan - stick to what you know, bring on partners with expertise, etc.

and please, the term "scamsics" is just dumb. I propose fakesics or fAkeSIC.

+1 

same here, looking forward to hearing more information - not necessarily from helveticoin, but from the business partners.

This is a multiple choice question. You are a manager in a reputable company that would like to remain reputable. Please choose which one of the following statements you could imagine saying publicly:

A) BFL is a scam.
B) BFL is real.
C) We have nothing to comment about our competitors.

Go easy on yerself Bruno...you've spotted AT LEAST 20 of the last ten scammers str8 away!

Concur, with apologies. There's so much shit going around lately, that...

But that's no excuse for my actions in this regard.

~Bruno K~

Im counting on this and waiting for with the great interest more info - hopefully they will be able to get good integrators and we´ll see new products by the summer.

It seems to me they are saying they know nothing of lightening, prime, and russian/chinese ASICs which people have likely been asking. I don't think they mean they have no idea what BFL or Avalon are doing-they have said their chips will out perform other offerings, so that suggests they know what is out there soon will be.

They have also said they will provide specs and test boards to selected integrators who have signed up with an NDA. SO hard to scam somebody when you have sent them a reference board to study.

Hopefully they release more info next week and plenty of proof. I think these guy will come good with product.

For a second there, Mr. Teal, I was sweatin' bullets, thinking that I was in error, but...


Compare the above with the below (gleaned from the OP of this thread).


That's what I'm in reference to. They imply that they have limited knowledge of other ASIC-based bitcoin mining outfits, yet are going to develop 28nm chips to directly compete with the competition, that they don't know anything and everything about.

They clearly have a command of the English language, yet constantly make simple grammatical errors. Did I not get the memo that proofreading is no longer in vogue?

True, they're not coming here asking for funds, but I do wonder what's being asked of those behind closed doors. And if that's the case, then I'll have to admit that I like them, for at least they're scamming outside the BT box.

I don't know any company that throws a few hundred K around just for laughs. These days big & small companies count every penny even more than they did in the past. Share holders have been burnt by the GFC and are screaming for profits and share price increases.

However I see where you are going-they have the resources to do a study on what they could make, and the business case. Some might even have good manufacturing costs they can leverage to make entry easier. But no big business will start a project with out a profitable business case, and it has to be more profitable than other projects they could invest that R&D in.

I'm hoping somebody quite large takes on these 28Nm ASICs. Somebody with nice low PCB manufacturing and assembly costs who can deliver in volume. Down side is that smart business means they will only slightly under cut BFL etc in cost for performance, but we would still get quality ASICs with a steady supply.
I'm also looking forward to different applications for these chips. PCI-E card based ASICs, all in one CPU motherboard with ASICs lined all over the board, server rack systems.

So next week is the first "press release" with target performance and the names of the chosen integrators??