Topic: Looking for system integrators for new asic - page 6. (Read 21920 times)

I think you've misunderstood what they're looking for.  They're just making chips and won't be supplying anything to end users.  They're looking for companies who want to get into the ASIC market without having to develop their own chips - how each company utilises those chips will determine which company's products offer the best value for end users.  There'll basically be 3 or 4 companies designing their product around the same chip - just like many companies use Intel's chips for their products.

The advantage to the companies is that they're starting off with a 28 nm chip which will be improved upon over time and not having to pay the chip development costs.  Smaller chips are one of the things which will inevitably happen with other ASIC developers, but not until they've recovered their R&D costs on their first generation and made a considerable profit to boot.  

It's unlikely this is going to be the only B2B chip producer to enter the ASIC market.  If these guys are for real, it signals the beginning of real competition in the ASIC market.

I've always hoped that there were a couple of organisations developing ASICs under the radar.  Let's hope this one is legitimate.  Sounds like they're doing what Avalon originally hoped to do.

thank you helveticoin for providing EU ASICs. can't wait to be your customer

Allow me reiterate the purpose of this post was to get in contact with potential manufacturing partners (and as such, it is proving to have been very worthwhile), not to find funding, secure pre orders or satisfy everyone's curiosity. As a rule of thumb,  I will divulge information in so far it helps potential partners determine if its worth their while to talk to us,  but providing implementation details would not achieve that and might expose details Im not comfortable sharing. So Im not willing or able to elaborate on the questions posted above, even if  I do feel that applying some common sense would answer most of them.

As for our website, its near the bottom of our long todo list, and if we get around making one, dont expect to find lots of personal or technical details. I hinted at the reasons for the former,  and we will leave it to our partners to announce their products and provide you with their technical specifications, performance,  time tables and prices at the time they deem appropriate.

edit: what RHA said.

The questions about website, price etc. are for the system integrators which are looked for, not for helveticoin. The integrator(s) will offer the miners, so wait a few months.

Yes, How about a website with more details? About the team, their background and expertise. Sounds interesting, but more specifics are needed.
Regards,
Brian

Can you comment without an NDA on the design of the ASIC?
Do you use a rolled or unrolled design?
Is the hashing logic hand optimized or does it use standard cell libraries?

I'd be a willing beta tester,lol.

Ill be interesting funding or even buying bulk orders if you are saying is going to be competitive and very interested in getting in contact with you to have a chat.

If you are saying what is true, How long befor you have a website up with some product information pricing shipping etc?

BFL is 65nm correct? So this chip would have (65/28)2= ~5.4x higher density. So all other things being equal, you would expect at least 5x the performance per mm2 or per wafer. Factor in SOI and higher clockspeeds and it might be 6-7-8x?  Ignoring fixed costs, how can this be more expensive per GH than BFL? Is SOI really that expensive?

At this rate you might beat BFL to market.

OK, I apparently misunderstood what it meant to be a "slave chip".
So, yaeh, if the "slave mode" actually works as advertised this may be a very competitive entry. The NRE costs are spread over multiple designs from the same European ASIC house. Just consider the entire Cortex-M3 a single large "defect" when estimating yield, because it only occupies a neglible portion of the chip area. I'm going to make an assumption that the designers were sane and they provided individual "clock enable" bits for the subregions of the hashing region of the chip so that the defect of a single hashing core doesn't disqualify a whole chip.

I always consider it a good sign when vendor gives a forthcoming and reasonable explanation for a misfeature or a drawback.

I wish good luck to everyone involved.

Edit: If you could answer one more question without an NDA: does the SoC have some analog circuitry to measure the temperature of the chip? Or at least there is some circuitry attached to some pin that will allow to build a temperature-to-leakage,leakage-to-time,time-to-digital termometer for the chip proper?

Thanks.

First Id like to thank (most of) the people that contacted me via email. I will get back to you once I return to my office and after I got the green light from our legal counsel regarding the non disclosure agreements, then we can discuss how to move forward.

As for some of the comments on this forum; Im not sure I understand all the questions or remarks, but to clarify, we are not looking for funding. Our operation is fully funded. If anyone wants to see our chips, a demo can be arranged as mentioned above, but it will require you sign an NDA.

As for our competitiveness; our approach certainly isnt the cheapest, but unit production cost of asics is only a tiny fraction of current retail value of asic based miners, and is typically measured in single or low double digits.  So even if our chip cost 5x or 10x  more per GH than those of our colleagues (which it doesnt), our partners will have no trouble competing with other end user solutions.  Over time we expect retail prices to drop low enough for per chip production costs to become a handicap, but only after difficulty has increased tremendously. At that point power efficiency will again become a key selling point, and that is where we have our largest advantage,  so I feel we and our partners will be able to remain competitive no matter what for the foreseeable future.

Lastly, about our decision to implement an ARM core; this was driven primarily for reasons unrelated to bitcoin. One might even say we decided to add a bitcoin miner to some ARM test chips. However, this isnt a handicap.  Even though this tiny core clocks higher than you probably think, the core has its own clock domain and voltage plane. As I indicated earlier, the bitcoin miner can operate with or without the ARM core, and the latter only occupies a negligible portion of our transistor budget. It does use a more significant part of the IO connectors, but the flipside of that will be cheaper PCBs and overall  the chip still has a very low ball pitch.  In short; if you dont like it, just pretend it isnt there and feel free to add an external soc of your choosing.

This is a very serious design mistake to mix up the hashing units and their controller on a single chip.

The primary problem is that anytime there is a internal miscompare detected it is impossible to distinguish the hasher failure from the controller failure. Therefore the whole design will have to be run at a fixed voltage and fixed frequency far away from the limits of the 28nm manufacturing process.

In addition to the above problem you'll suffer from the standard problems of manufacturing a chip containing complex circuitry like a SOC:

1) relatively low yield when compared to a repetitive chip like hashers,
2) you'll actually have to develop and pay for proper test of each manufactured chip unlike the hashers that are pretty much self-testing,

Finally, Cortex-M architecture doesn't run normal Linux because of the lack of the MMU that is included in Cortex-A chips that are popular tragets for Linux on ARM. It is possible to run some cut-down Linux on the MPU that is available in Cortex-M processors.

On the positive side Cortex-M is more resilient than Cortex-A in the presence of power-supply ripple and the extremes of the chip temperatures. The first circuitry to fail when overclocking/undervolting ARM is the MMU. So you'll be able to live somewhat closer to the edge of the process.

Another example of why decades of experience are no match for one year of clear thinking.

I doubt that the hasher portion of the chip has enough connectivity to the pins to be able to run it separately on a chip where Cortex-M3 failed the tests. But it may be possible to fill out all the available code memory of Cortex-M3 with multiple implementations of a trivial hasher driver that uses various instruction sequences. When the CPU portion of the chip fails it may still execute properly only some of the instructions or the code where every other instruction is a NOP.

The last time I had information about per-instruction failure rates was for Intel 80386 chips. An example of permanent manufacturing failure: certain 32-bit multiplications failed. If you only used 16-bit multiply everything was working fine. An example of temporary failure due to overclocking/undervolting: POP SS failed. But if you had a code than never modified the stack segment register it would work fine, so the CPU was useable if the whole code&data fit within 64kB and the segment registers were never modified.

As a software developer you may be able to develop a similar set of rules and workarounds for Cortex-M. As a partner just design a large PCB where single Cortex-A SOC running proper Linux controls the multitude of those Cortex-M & hasher chips.

Wow.  I've never been tipped before.  15BRMpNev4p264f1M3npns7VfB1BFTWzf7 will do.

Because

Why not to look at these great 28nm chips first? 

The most important metric in current market is not power efficiency (Hash/J), but simply price per Hash/s. Sounds like you are far behind the competitors.
Another detail to note is that your professionally written call for partners is posted in a fucking internet forum. Any group of graduate students in Switzerland would be a better place to look for the solution you need, not to mention simple advertisement on a professional Website or in a journal, or even LinkedIn. I suspect this has got something to do with users of this forum having a proven competitive advantage compared to other groups I listed when it comes to sending advance payments to random story-tellers.

I can act as bounty hunter in case they don't deliver Good luck with your business.

Lol

To which address do I tip BTC?