That's still only accounting for the simultaneous nonce problem, not the similar bitmask or zero bitmask cases. You certainly make a good argument for not using atomic ops.
No bitmasking needed, the C "?" operator has a specific GPU ISA op code.
Quote
OCL: (phatk vectors 2 example)
(...)
#elif defined VECTORS2
uint result = W[117].x ? 0u:W[3].x; //if(!W[117].x) result=W[3].x; else result=0;
result = W[117].y ? result:W[3].y; //if(!W[117].y) result=W[3].y; /*else result=result;*/
if (result) //result can only be 0 or a nonce: W[3].x or W[3].y
SETFOUND(result);
(...)
GPU ISA:
(...)
1349 z: ADD_INT T3.z, PV1348.x, T0.x
w: ADD_INT ____, PV1348.y, T0.w
1350 y: CNDE_INT ____, PV1349.w, R18.w, 0.0f
1351 x: CNDE_INT R2.x, T3.z, R17.z, PV1350.y
1352 x: PREDNE_INT ____, R2.x, 0.0f UPDATE_EXEC_MASK UPDATE_PRED
66 JUMP POP_CNT(1) ADDR(76)
(...)
(...)
#elif defined VECTORS2
uint result = W[117].x ? 0u:W[3].x; //if(!W[117].x) result=W[3].x; else result=0;
result = W[117].y ? result:W[3].y; //if(!W[117].y) result=W[3].y; /*else result=result;*/
if (result) //result can only be 0 or a nonce: W[3].x or W[3].y
SETFOUND(result);
(...)
GPU ISA:
(...)
1349 z: ADD_INT T3.z, PV1348.x, T0.x
w: ADD_INT ____, PV1348.y, T0.w
1350 y: CNDE_INT ____, PV1349.w, R18.w, 0.0f
1351 x: CNDE_INT R2.x, T3.z, R17.z, PV1350.y
1352 x: PREDNE_INT ____, R2.x, 0.0f UPDATE_EXEC_MASK UPDATE_PRED
66 JUMP POP_CNT(1) ADDR(76)
(...)
So, refactoring...
