Why not just download the ISE from webpack and doing some dry runs on the code? The software will tell you the device utilisation and the expectable performance numbers and the functionl correctness can be tested before.
For mining there could with the current code base some better suited boards, but this can change with better designs.
Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 36. (Read 432950 times)
June 24, 2011, 08:23:56 AM
June 24, 2011, 07:09:36 AM
I ve been looking for another developement board and got interested in this one xilinx Spartan 6
http://shop.trenz-electronic.de/catalog/product_info.php?products_id=830
As i asume the LE's of altera and xilinx to be equivalent this should be abled to run the xilinx version of teknohog an full scale or are there any other limitations than routing ?
If nobody has objections ,i will order it and be ready to help improving the code after my exams in august.
http://shop.trenz-electronic.de/catalog/product_info.php?products_id=830
As i asume the LE's of altera and xilinx to be equivalent this should be abled to run the xilinx version of teknohog an full scale or are there any other limitations than routing ?
If nobody has objections ,i will order it and be ready to help improving the code after my exams in august.
June 24, 2011, 04:56:09 AM
Thanks, it work fine,
but i get only 6.253394 MH/s
My FPGA is Virtex IIPro XC2VP50 and project settings are:
miner clock frequency = 50 MHz
DEPTH = 3
In your opinion, is 6 MH/s correct value for this project settings?
or did I do something wrong?
but i get only 6.253394 MH/s
My FPGA is Virtex IIPro XC2VP50 and project settings are:
miner clock frequency = 50 MHz
DEPTH = 3
In your opinion, is 6 MH/s correct value for this project settings?
or did I do something wrong?
DEPTH = 3 means 2^3 = 8 pipeline stages for the 64 SHA256 rounds, so each nonce will take 64 / 8 = 8 clock cycles. At 50 MHz that's 50 / 8 = 6.25 MH/s.
June 24, 2011, 02:49:13 AM
Yes, this values should be correct, i get with LOOP=3
8 MHash/s @ 65 MHz on a EP2C35C8 (Fmax=63 MHz)
14 MHash/s @ 85 MHz on a EP3C25C6
both with the original code from fpgaminer
8 MHash/s @ 65 MHz on a EP2C35C8 (Fmax=63 MHz)
14 MHash/s @ 85 MHz on a EP3C25C6
both with the original code from fpgaminer
June 24, 2011, 01:33:02 AM
Thanks, it work fine,
but i get only 6.253394 MH/s
My FPGA is Virtex IIPro XC2VP50 and project settings are:
miner clock frequency = 50 MHz
DEPTH = 3
In your opinion, is 6 MH/s correct value for this project settings?
or did I do something wrong?
but i get only 6.253394 MH/s
My FPGA is Virtex IIPro XC2VP50 and project settings are:
miner clock frequency = 50 MHz
DEPTH = 3
In your opinion, is 6 MH/s correct value for this project settings?
or did I do something wrong?
June 23, 2011, 10:58:12 AM
June 23, 2011, 09:07:14 AM
Yes, it's a curses error, most likely being caused by the terminal window being too small to draw the summary box at the top.
You're right, I increase terminal window size and now it work.Depending on the length of your pool names the current version will need around 120 chars of width, the older one in the git repository maybe a bit less.
What is a current version? This? http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.1.zip June 23, 2011, 06:30:55 AM
to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:
What it means?
I run it on Debian 6.0, Python 2.7.2
it has some thing to do with curses.Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:
Code:
root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
File "miner.py", line 478, in
curses.wrapper(miner.run)
File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
return func(stdscr, *args, **kwds)
File "miner.py", line 380, in run
self.showstats()
File "miner.py", line 290, in showstats
self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR
Traceback (most recent call last):
File "miner.py", line 478, in
curses.wrapper(miner.run)
File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
return func(stdscr, *args, **kwds)
File "miner.py", line 380, in run
self.showstats()
File "miner.py", line 290, in showstats
self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR
What it means?
I run it on Debian 6.0, Python 2.7.2
try a different terminal maybe, i don't know.
Yes, it's a curses error, most likely being caused by the terminal window being too small to draw the summary box at the top.
Depending on the length of your pool names the current version will need around 120 chars of width, the older one in the git repository maybe a bit less.
June 22, 2011, 06:36:53 PM
So if i would compare a Altera Cyclon III with 55k macrocells
http://de.farnell.com/altera/ep3c55u484c7n/fpga-cyclone-iii-55k-le-484ubga/dp/1742170
to a Xilinx Spartan 3 with roughly 53k macrocells
http://de.farnell.com/xilinx/xc3sd3400a-4csg484i/fpga-spartan-3a-dsp-484csbga/dp/1876218
The Xilinx would be a lot slower than the altera due to the routing problem using the current code altough they both have almost the same number of Elements.
Or am i mistaken here ?
Has anyone tested one or both of this chips and may supply Mh/s or similiar data for performance comparison ?
Itmight be interesting if the lower performance of the xilinx chips is caught up by theri lower prices.
The other thing is : How do the chips of the different families differ if they have the same number of elements eg between cyclone III and IV ?
http://de.farnell.com/altera/ep3c55u484c7n/fpga-cyclone-iii-55k-le-484ubga/dp/1742170
to a Xilinx Spartan 3 with roughly 53k macrocells
http://de.farnell.com/xilinx/xc3sd3400a-4csg484i/fpga-spartan-3a-dsp-484csbga/dp/1876218
The Xilinx would be a lot slower than the altera due to the routing problem using the current code altough they both have almost the same number of Elements.
Or am i mistaken here ?
Has anyone tested one or both of this chips and may supply Mh/s or similiar data for performance comparison ?
Itmight be interesting if the lower performance of the xilinx chips is caught up by theri lower prices.
The other thing is : How do the chips of the different families differ if they have the same number of elements eg between cyclone III and IV ?
June 22, 2011, 04:12:00 PM
How would something like a Papilio stack up to the cards being used in this thread?
http://papilio.cc/
Is it laughably underpowered?
Looks like it's a Spartan 3E chip on board, but it appears to be a cheap stripped down FPGA
http://papilio.cc/
Is it laughably underpowered?
Looks like it's a Spartan 3E chip on board, but it appears to be a cheap stripped down FPGA
June 22, 2011, 11:02:29 AM
to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:
What it means?
I run it on Debian 6.0, Python 2.7.2
it has some thing to do with curses.Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:
Code:
root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
File "miner.py", line 478, in
curses.wrapper(miner.run)
File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
return func(stdscr, *args, **kwds)
File "miner.py", line 380, in run
self.showstats()
File "miner.py", line 290, in showstats
self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR
Traceback (most recent call last):
File "miner.py", line 478, in
curses.wrapper(miner.run)
File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
return func(stdscr, *args, **kwds)
File "miner.py", line 380, in run
self.showstats()
File "miner.py", line 290, in showstats
self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR
What it means?
I run it on Debian 6.0, Python 2.7.2
try a different terminal maybe, i don't know.
June 22, 2011, 09:54:59 AM
to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:
What it means?
I run it on Debian 6.0, Python 2.7.2
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:
Code:
root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
File "miner.py", line 478, in
curses.wrapper(miner.run)
File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
return func(stdscr, *args, **kwds)
File "miner.py", line 380, in run
self.showstats()
File "miner.py", line 290, in showstats
self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR
Traceback (most recent call last):
File "miner.py", line 478, in
curses.wrapper(miner.run)
File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
return func(stdscr, *args, **kwds)
File "miner.py", line 380, in run
self.showstats()
File "miner.py", line 290, in showstats
self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR
What it means?
I run it on Debian 6.0, Python 2.7.2
June 22, 2011, 09:00:54 AM
maybe the guys talking about ASIC should start a new thread about ASIC mining.
no offence. but the thread is about FPGA mining. i really like guys who haves bit idea for bitcoin mining, but you are getting offtopic now.
no offence. but the thread is about FPGA mining. i really like guys who haves bit idea for bitcoin mining, but you are getting offtopic now.
June 22, 2011, 08:51:06 AM
Hi all,
I finally joined today to participate in this development. I am an experienced ASIC designer turned game programmer. I just started looking at the source code, hopefully will be contributing to the improvement of the core soon.
Question to others, have you considered pooling together to tape out an ASIC? A TSMC shuttle wouldn't cost 1 million. I can do the ASIC, but I lack the PCB board design knowledge. I can do it, but it'll probably have a short somewhere.
___________________________________________________________
Donate to me at: 1PNkxttFgUzvaMjmnzEU5dbviSiv9qkHBp
I finally joined today to participate in this development. I am an experienced ASIC designer turned game programmer. I just started looking at the source code, hopefully will be contributing to the improvement of the core soon.
Question to others, have you considered pooling together to tape out an ASIC? A TSMC shuttle wouldn't cost 1 million. I can do the ASIC, but I lack the PCB board design knowledge. I can do it, but it'll probably have a short somewhere.
___________________________________________________________
Donate to me at: 1PNkxttFgUzvaMjmnzEU5dbviSiv9qkHBp
I have done some VLSI development, but it was full custom (ie hand-drawn layout using magic, rather than place and route RTL / standard cells). We used MOSIS (www.mosis.com) which does "multi-project wafer runs" to keep costs down. Back in 2001 we got a chip made using a 0.18um TSMC CMOS process. Ended up costing around $50k for 50 chips, although not all of them were packaged. The RTL used on this FPGA project could be used by yourself as a starting point to produce an ASIC design. I would then recommend looking into optimizing the adder structures making use of CSA and CLA techniques. Then some decisions need to be made about the external I/O.
June 22, 2011, 04:51:09 AM
I would like to know if the Spartan 3 series with 1000 gates is capable of running this fpga Miner software?
As magik allready tested it seems to me that the xilinx chips need a very different code structure. In wich way there would be modification nescesary?
As magik allready tested it seems to me that the xilinx chips need a very different code structure. In wich way there would be modification nescesary?
I ported the original FPGA miner to a Spartan 3E with 500K gates, so if you mean 1000K gates, it is certainly possible. The original was tied to Altera chips, here is my version for Xilinx with serial port communications:
https://github.com/teknohog/Xilinx-Serial-Miner
I had to keep the parameter LOOP_LOG2 at 5 for minimum unrolling, and I get 3 Mhash/s at 100 MHz. With bigger chips you should be able to decrease this for more unrolling and better hashrates.
However, a general issue with Xilinx seems to be that these designs need a lot of routing, so you run out of wires when trying to use all of the gates. Altera seems better in this respect.
Some of the others seem to be working on these issues with different designs. I have not yet touched the actual hashing code, I merely did the minimum to get this running on a Spartan.
June 22, 2011, 03:53:23 AM
Hello everybody
As i am reentering this topic afther some years i would like to as some questions:
I would like to know if the Spartan 3 series with 1000 gates is capable of running this fpga Miner software?
As magik allready tested it seems to me that the xilinx chips need a very different code structure. In wich way there would be modification nescesary?
I would like to know in wich way the LE's of Altera are comparable to the gates of Xilinx?
Were may i get basic literature about the laguages you use in this development ? ( last time i programmed such devices we allways used assembler code)
I hope i may contribute something to this very interesting project even with my rusty an humble knowledge
As i am reentering this topic afther some years i would like to as some questions:
I would like to know if the Spartan 3 series with 1000 gates is capable of running this fpga Miner software?
As magik allready tested it seems to me that the xilinx chips need a very different code structure. In wich way there would be modification nescesary?
I would like to know in wich way the LE's of Altera are comparable to the gates of Xilinx?
Were may i get basic literature about the laguages you use in this development ? ( last time i programmed such devices we allways used assembler code)
I hope i may contribute something to this very interesting project even with my rusty an humble knowledge
June 21, 2011, 06:25:17 AM
I believe I'm using your master branch. I did try one of your broken branches: I was able to get 100 MHz with CONFIG_LOOP_LOG2=2! I knew it didn't make any sense, but I went ahead and tried it anyways. Of course all my submits were rejected.
In that case, you're actually running fpgaminer's unmodified code. (There are technical reasons why I have that as the master branch on my git repository.) Still surprised you managed to reach 80 MHz though...Edit: Also, at some point I should modify my newer changes to properly allow less loop unrolling and see how well that works. Not sure how effective it would be though, and it's a pain to get right.,
June 20, 2011, 11:23:59 PM
I decided to do some testing to see if I could get a better estimate of my hashing power. I modified mine.tcl to poll my hashrate (based on a 10 minute average) from deepbit every time I timeout searching for a golden ticket (so approximately every 20 seconds). I then average my polls to get an estimate.
After about 4 hours of running my estimate is ~ 13 MH/s. Looks like I was just getting lucky earlier
I believe I'm using your master branch. I did try one of your broken branches: I was able to get 100 MHz with CONFIG_LOOP_LOG2=2! I knew it didn't make any sense, but I went ahead and tried it anyways. Of course all my submits were rejected.
After about 4 hours of running my estimate is ~ 13 MH/s. Looks like I was just getting lucky earlier
I'm running makomk's branch on a DE2 (not -115) at 80MHz with CONFIG_LOOP_LOG2=3. I should be able to run at at least 90MHz because I have plenty of slack but I haven't had the time to look into that yet. At the moment, setting a higher frequency causes "Place & Route" to do worse instead of better.
Should be 10 megahash/sec in theory, yeah. I'm surprised you managed to reach 80MHz though. Just to check, you're not running one of my older branches that's broken with CONFIG_LOOP_LOG2!=0? They should all be clearly labelled and it would probably be obvious if you were because you wouldn't get any shares, but still...I believe I'm using your master branch. I did try one of your broken branches: I was able to get 100 MHz with CONFIG_LOOP_LOG2=2! I knew it didn't make any sense, but I went ahead and tried it anyways. Of course all my submits were rejected.
June 20, 2011, 11:14:16 AM
I'm running makomk's branch on a DE2 (not -115) at 80MHz with CONFIG_LOOP_LOG2=3. I should be able to run at at least 90MHz because I have plenty of slack but I haven't had the time to look into that yet. At the moment, setting a higher frequency causes "Place & Route" to do worse instead of better.
Should be 10 megahash/sec in theory, yeah. I'm surprised you managed to reach 80MHz though. Just to check, you're not running one of my older branches that's broken with CONFIG_LOOP_LOG2!=0? They should all be clearly labelled and it would probably be obvious if you were because you wouldn't get any shares, but still...Not sure if anyone here is using Stratix IV, but I have managed to compile a design with 4 SHA256 pairs for the EP4SE530 (2nd largest Stratix IV device). The resource usage is at 68% and clock rate is 195MHz, to give a total hash rate of 780Mh/s. I'm now trying to compile with 6 SHA256 pairs. Not sure that will fit, but 5 definitely will, so a single Stratix IV is good for approximately 1Gh/s.
The code can be found at: https://github.com/OrphanedGland/Open-Source-FPGA-Bitcoin-Miner
Ooh, neat, thanks! Stratix IV is well outside my price range - and probably most people's, to be fair - but it's interesting to see what can be achieved in theory. Some very unusual optimisations there too.The code can be found at: https://github.com/OrphanedGland/Open-Source-FPGA-Bitcoin-Miner
Edit: Aha, that's what you meant by precomputing H+K+W! I'd unimaginatively named the equivalent register t1_part...
June 20, 2011, 08:09:11 AM
Not sure if anyone here is using Stratix IV, but I have managed to compile a design with 4 SHA256 pairs for the EP4SE530 (2nd largest Stratix IV device). The resource usage is at 68% and clock rate is 195MHz, to give a total hash rate of 780Mh/s. I'm now trying to compile with 6 SHA256 pairs. Not sure that will fit, but 5 definitely will, so a single Stratix IV is good for approximately 1Gh/s.
The code can be found at: https://github.com/OrphanedGland/Open-Source-FPGA-Bitcoin-Miner
The code can be found at: https://github.com/OrphanedGland/Open-Source-FPGA-Bitcoin-Miner
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