Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 38. (Read 432950 times)

I like this idea, however maybe it's a case of walking before you run?  Surely the flexibility of PCIe makes it useful in may cases, and adapting that to an all-in-one arm/linux unit is a small (and logical) next step.

I know I have two computers with spare PCIe slots that I'd use to start with, test it out, make sure it all works well.  Unless the arm/linux all-in-one miner is cheaper (by some measure)...

I think that not everyone who would consider buying an ASIC miner will want to have a dedicated machine for it - just like today not everyone has a dedicated GPU mining rig.

@TheSeven: maybe I am wrong, but I am currently not sure if pyfpgaminer is still having some issues.

Currently I have two fpga board, running in different physical locations.
Both boards are running different bitfiles.

If I now compare the outputs of pyfpgaminer, then on both consoles I see around 10% rejected shares.
If I match the consoles timewise, then the rejects happen at the same points in time.

Do you have any idea if that could be related to specific api calls or something within the communication with the pool?


A)

Found share: eligius:dd51c0630a1638ba8e819b38aa18183b7d4e8d98d5260805d82f3ba9b3fdcbf8:bb9e77d84df7598d1a1d932f:7a031f22       
eligius rejected share 7a031f22                                                                                               
Mining: eligius:f219c175c6f49f8ec2cf0b302307f4f439650c7886b7516ff06656ae84831717:dd20a1094df759a91a1d932f                     
Mining: eligius:098e08762b694e86849b98bb5cfb58289fab9647e9ee082973af9c3cc8dfc00f:27be68d44df759c51a1d932f                     
Found share: eligius:098e08762b694e86849b98bb5cfb58289fab9647e9ee082973af9c3cc8dfc00f:27be68d44df759c51a1d932f:6cfa9395       
eligius rejected share 6cfa9395   

B)
Found share: eligius:3f8347933e5369be01edc6f05284cdefce58f727e97ef6c9334bc8da642a4186:c87f6b0f4df759641a1d932f:0bb3d26f       
eligius rejected share 0bb3d26f                                                                                               
Mining: eligius:0c6933c15b68a5a1480f60382eaa95058eb8ddc3abf2629332c2bbbf05571b68:e3ea48fe4df7597f1a1d932f                     
Mining: eligius:956dfec46f309dfe46db73459267fd2ac3a7b30d54b4ea1e6b437c879a2ee739:84ebf8984df7599a1a1d932f                     
Mining: eligius:6a27c65613e41864db70feefdb8db812aecc86a6dedb6104b10f06acb20d7f2b:213e86ab4df759b71a1d932f                     
Mining: eligius:434201cd46a5972605ee6a5f2fa4baa12f68b73871b164b82597f3a817258bb2:2dd2aca84df759d21a1d932f                     
Mining: eligius:73347264657294419b1f2ce908373d775decd40116836091ceddc01b01492d5e:632383ca4df759ee1a1d932f                     
Found share: eligius:73347264657294419b1f2ce908373d775decd40116836091ceddc01b01492d5e:632383ca4df759ee1a1d932f:2b11428c       
eligius rejected share 2b11428c     

Don't suppose anyone wants to help me buy this? http://www.dinigroup.com/new/DNBFC_S12_12_Cluster.php

Looks like they only provide the IP and/or design services.   Perhaps we could get a KickStarter project up and pay them to develop it.

There is a comparison table on their site:
http://www.heliontech.com/fast_hash.htm

Anyone ecer had a look at http://www.heliontech.com/downloads/fast_hash_asic_datasheet.pdf

This looks quite impressive performance wise, if the numbers are vaguely comparable.

I fully agree. As I said, I would commit to quite some. 3 full boxex minimum if pcie compatble, more if not needed. Get me a timpline and a preliminary price and a form factor and Iam willing to deposit money into escrow.

Whatever the design, it needs to be cheap and ready soon.  You can bet there are lots of people working on private ASIC projects, which could obsolete everything.

Not sure that makes sense, though. This would mean a LOT (!) more isntances to manage, a lot more ethernet port to block. I would go backplane.

if we can use something like http://www.chassis-plans.com/single-board-computer/S6806-backplane.htm it gives us 20 PciE boards. Now, I would love to make as much use as possible out of this space

Why have servers at all? For a couple of dollars more, you could equip those boards with an ethernet port and a small ARM processor running linux, with a ready-to-go firmware preinstalled, which would be configured through a web interface. Or possibly a backplane with the ARM processor and ethernet, which has a couple of slots for crypto slave boards containing the ASICs.

Is that most efficient? As in: would a larger board not be better? Yes, it may cost more (even per mhash), but there is a not insignificant overhead to "host" the boards. Tiven the standard MSI / Sempron approach I think 5 or maybe 6 boards only could go on a motherboard. Having a higher density, especially given the low power consumption, would not be negative.

Then there is the whole driver issue at hand (sadly) Lokos like I would have to move to Linux.

Anyhow, I wuold be jumping on board if someone could start putting some plan together within this month (i.e. prices as you did, timeplan, nothing showing post 3 months timeframe). I would be willing to take anywhere between 3 and 10 servers full of boards, which to my knowledge would be between 15 and 50 More depends on the final numbers.

This would definitly change the market back to "commercial" miners, which I think is not a too bad thing - mining via gpu would not be cost efficient at all anymore. That said, it is definitly a good thing in my eyes - right now we have way too expensive mhash.

Heh, thank you njloof   I really appreciate that.

Quick update: I've been working with makomk's modifications and they do appear to be giving the performance increase and area reduction quoted. In fact, I saw ~75K LEs when I synthesized. Power consumption was estimated at 4.7Watts. Very impressive work! I'm doing another compile now and will do a live hardware test soon, to confirm correct share submission to mining pools.

EDIT: Just tested the new code on live hardware (DE2-115). Works great 

Assuming a 4"x6" board 4-layer board, the PCB itself would cost about 25$ a piece in low volume (100 pieces...that's from pcbexpress.com). If there's not too much routing, we could go for a 2-layer board which would be half the price. Cut that in half if we make 1000's.

Assuming there is less than 100 parts on the board, assembly of 100 boards is about 50$ per board (that's from aapcb.com). I usually assemble the first prototype(s) myself. Again, cut that in half if we make 1000's.

We really need to wait how the ASIC shapes up before making wild guesses on the required additional components on the board (regulators, oscillator, interface, etc.). However, I would be really surprise if this turns out to be more than 10-20$ per board depending how "stand-alone" is the board.

PCB design is free, I have all the tools.

Wow. Quartus II is claiming 108MHz and 78k LEs for my latest tweaks to the fully-unrolled DE2-115 code. I expect I could've hit at least 110MHz if the optimizer hadn't given up once it reached its 100MHz target. Surely this is too good to be true, especially since I haven't done anything fancy like precomputing W? Sadly I don't have a board to test this with but ModelSim seems to indicate it's not obviously broken. Anyway, it's up on github if you're feeling brave, and watch your cooling.

Edit:

The Cyclone II EP2C35 based one? Should be able to fit a partially-unrolled pipeline onto that in theory, though it probably wouldn't be massively fast. You'd have to port the HDL over to that board and compile a bitstream yourself, but that probably just means changing the device setting and pinout and turning down the level of loop unrolling.

(Edit 2: Apparently Fmax=110.34MHz for this design on the EP4CE115. Interesting. I think I should be able to improve on that a bit )

Does anyone know if code is available for the DE2 (not the DE2-115) board? I can get access to those through my university, so considering making it a summer project.

Was a fat finger error by a mod - thread is now unlocked.

Do you have a suggestion?
The only IC I could find that do SHA256 are kinda slow when looking at the throughput needed for mining. Sure you could chain a ton of them (they're cheap in lots of 1000) but the control logic surrounding it could get expensive.
The custom crypto-smashing machines so far have been FPGA or structured ASIC based. I think the one that cracked the RC4 challenge was like $250K worth or something.

Great project(s) and discussion here.


I've written a document that proposes a directory structure for FPGA designs that is version control friendly and scalable:

  https://www.boldport.com/docs/fpgaproj

Also, my (new) project

  http://www.boldport.com

generates build environments for FPGA projects. It uses Makefiles instead of the IDE GUIs and maintains the structure defined in the document above.

I'm happy to help and contribute to any FPGA project that wants to use the structure and/or "boldport flow". (Any feedback on the structure, and boldport, would be greatly appreciated!)

cheers,
saar. http://www.saardrimer.com

Maybe a stupid question, but why can't existing crypto hardware acceleration chips be used? Why does a new one have to be built?