[RELEASE] Avalon Reference | Bitcointalksearch.org

RamirezX

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Activity: 36

Merit: 10

Quote from: intron on May 27, 2013, 09:41:20 AM

The datasheet is rather vague on some points. The HDL
would help very much. Or probing a running ASIC on a board...

intron

Yes .. i read datasheet and I couldn't find, how the report n, p timing is done.
Friend of mine has sample chip, he can send config and sample data into chip, it calculates golden nonce, but output has some strange timing. It look like it's derived of external oscillator frequency, but how?

ProfMac

legendary

Activity: 1246

Merit: 1002

Quote from: samurai1200 on May 10, 2013, 01:54:16 AM

Let the hardware dev shitstorm commence!!!

Downloading altium viewer now Sad

I just registered for the altium viewer.
Has anyone made a CadSoft EAGLE version of these documents?

daemondazz

sr. member

Activity: 448

Merit: 250

Sample chips will be big news when they start arriving.

Does anyone know an actual part number for the magnetic beads for each chip? The BOM says 60ohm@100MHz, but doesn't give a current rating.

HorseRider

donator

Activity: 1120

Merit: 1001

anyone got any news on the sample chips??

intron

sr. member

Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Quote from: ppcko on May 27, 2013, 09:32:39 AM

Quote from: intron on May 27, 2013, 08:19:42 AM

Is the verilog/VHDL code for the FPGA also open source? Very
curious how they did the communication with the ASICs.

intron

Only binary version at this moment. Open source version of VHDL should be released later.
Also, check the git repository. Avalon datasheet is available there. Maybe you'll find what are you looking for in it.

From the readme file (https://github.com/BitSyncom/avalon-ref/blob/master/README.md):
disclaimer:
==========
current version of FPGA bitstream contains licensed parts we can not open source
at the moment,
a licensed free version is being worked on that will be released in the future.

The datasheet is rather vague on some points. The HDL
would help very much. Or probing a running ASIC on a board...

intron

ppcko

newbie

Activity: 16

Merit: 0

Quote from: intron on May 27, 2013, 08:19:42 AM

Is the verilog/VHDL code for the FPGA also open source? Very
curious how they did the communication with the ASICs.

intron

Only binary version at this moment. Open source version of VHDL should be released later.
Also, check the git repository. Avalon datasheet is available there. Maybe you'll find what are you looking for in it.

From the readme file (https://github.com/BitSyncom/avalon-ref/blob/master/README.md):
disclaimer:
==========
current version of FPGA bitstream contains licensed parts we can not open source
at the moment,
a licensed free version is being worked on that will be released in the future.

intron

sr. member

Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Quote from: samurai1200 on May 10, 2013, 12:19:21 PM

Quote from: SebastianJu on May 10, 2013, 12:16:56 PM

Quote from: samurai1200 on May 10, 2013, 12:10:35 PM

Quote from: SebastianJu on May 10, 2013, 11:54:29 AM

Can someone with enough knowledge tell me if a user that has avalon chips, can take this plans and let a company create a miner for him? Is it possible or is more needed?

Can it be done DIY, if you manage to get the parts?

And the software, firmware and so on is it freely available? I guess the miners that run with avalons would run with this miner too, right?

Today/this weekend, I'm going to investigate the building out of units based precisely on the reference design, and see if it'd be worth it to organize a group buy. This is hopefully assuming that Bitsyncom will be providing software. I haven't had a chance to look at the schematics in depth, but I didn't see a microcontroller, but rather an FPGA. Reverse-engineering what's happening inside it would probably prove to be a major pain.

An fpga sound expensive. The other miner developers dont need one. For example the klondike-project (see my signature). So im really wondering if the alternate design will be cheaper than the original one at the end. Interesting this all...

It's just for control and data pre-processing. It's not for hashing.

$24.27/pc in single quantities.
http://www.digikey.com/scripts/dksearch/dksus.dll?vendor=0&keywords=XC6SLX16-2FTG256C&stock=1

Is the verilog/VHDL code for the FPGA also open source? Very
curious how they did the communication with the ASICs.

intron

ScaryHash

hero member

Activity: 529

Merit: 501

What did you use? I tried KiCad, but it did not work... Huh

rassalas

newbie

Activity: 30

Merit: 0

Quote from: rassalas on May 26, 2013, 10:53:09 AM

Quote from: BkkCoins on May 24, 2013, 07:15:06 PM

Quote from: rassalas on May 24, 2013, 06:40:42 PM

Quote from: BitSyncom on May 09, 2013, 09:42:22 PM

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question, I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files.
I'm assuming the BOM files were also generated by the same Cad program. Anyone know?
Rassalas

Altium Designer. They do have a free viewer for Windows on their web site. No Linux sadly.

I don't think Altium is what was used. We can't seem to load the SCHDOC nor the PCBDOC files with Altium designer.
If I'm wrong, please do elaborate.
Thank you

I stand corrected. We got them loaded. looking nice.

rassalas

newbie

Activity: 30

Merit: 0

Quote from: BkkCoins on May 24, 2013, 07:15:06 PM

Quote from: rassalas on May 24, 2013, 06:40:42 PM

Quote from: BitSyncom on May 09, 2013, 09:42:22 PM

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question, I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files.
I'm assuming the BOM files were also generated by the same Cad program. Anyone know?
Rassalas

Altium Designer. They do have a free viewer for Windows on their web site. No Linux sadly.

I don't think Altium is what was used. We can't seem to load the SCHDOC nor the PCBDOC files with Altium designer.
If I'm wrong, please do elaborate.
Thank you

grabber

member

Activity: 67

Merit: 10

Awesome release! Thanks!

ecliptic

sr. member

Activity: 322

Merit: 250

iirc they made PDFs of the schematics, but i think they forgot and made it only of say, page #2 of a 2 page document, on some of them

the gerbers should be able to be viewable at least

el_rlee

legendary

Activity: 1600

Merit: 1014

Quote from: BkkCoins on May 24, 2013, 07:15:06 PM

Quote from: rassalas on May 24, 2013, 06:40:42 PM

Quote from: BitSyncom on May 09, 2013, 09:42:22 PM

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question, I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files.
I'm assuming the BOM files were also generated by the same Cad program. Anyone know?
Rassalas

Altium Designer. They do have a free viewer for Windows on their web site. No Linux sadly.

And the viewer is not free... gotta register.

BkkCoins

hero member

Activity: 784

Merit: 1009

firstbits:1MinerQ

Quote from: rassalas on May 24, 2013, 06:40:42 PM

Quote from: BitSyncom on May 09, 2013, 09:42:22 PM

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question, I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files.
I'm assuming the BOM files were also generated by the same Cad program. Anyone know?
Rassalas

Altium Designer. They do have a free viewer for Windows on their web site. No Linux sadly.

rassalas

newbie

Activity: 30

Merit: 0

Quote from: BitSyncom on May 09, 2013, 09:42:22 PM

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question, I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files.
I'm assuming the BOM files were also generated by the same Cad program. Anyone know?
Rassalas

BkkCoins

hero member

Activity: 784

Merit: 1009

firstbits:1MinerQ

Quote from: fpgaminer on May 16, 2013, 08:59:47 PM

Quote

At difficulty 1 the target will be: 0x00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Which is 32 leading zeros. This divides the 256-bit hash space in 2^32 segments. This means on average one out of every 2^32 hashes will be a valid share. So one Avalon chip at 256Mh/s will return a valid share once every 16 seconds.

Yup, you've got it right.

Yes, except the Avalon is designed to do partial nonce ranges. So in practice you give each one a start nonce value and let it run some period suitable for the none to reach the value of the next range, after which it's wasting cycles. The controller needs to know when a range should be done and send more work. This divides the total nonce time by the number of Avalon in a chain.

fpgaminer

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Activity: 560

Merit: 517

Quote

At difficulty 1 the target will be: 0x00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Which is 32 leading zeros. This divides the 256-bit hash space in 2^32 segments. This means on average one out of every 2^32 hashes will be a valid share. So one Avalon chip at 256Mh/s will return a valid share once every 16 seconds.

Yup, you've got it right.

goodney

member

Activity: 102

Merit: 10

Quote from: fpgaminer on May 16, 2013, 03:38:35 PM

Quote

How do you set the difficulty for the shares? Or is it fixed?

You don't; all core mining algorithms designed to-date work to solve difficulty 1, as do these ASICs. The controlling software is responsible for filtering out shares that don't meet the required difficulty.

Thanks... help me out here to clarify my thinking:

At difficulty 1 the target will be: 0x00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Which is 32 leading zeros. This divides the 256-bit hash space in 2^32 segments. This means on average one out of every 2^32 hashes will be a valid share. So one Avalon chip at 256Mh/s will return a valid share once every 16 seconds.

-a[g

strombom

member

Activity: 77

Merit: 10

Quote from: goodney on May 16, 2013, 02:13:14 PM

Also, is the HDL code for the FPGA coming?

Looking at point 10 it seems like the HDL code will be open source: http://store.avalon-asics.com/?page_id=9605

SebastianJu

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Quote from: fpgaminer on May 16, 2013, 03:56:16 PM

Quote

I dont have any experience but wouldnt that mean there is hashpower going lost when it calculates things that cant be used and thrown away?

Nope; and besides, all mining algorithms work this way.

Now i remember... the difficulty was no var in hashing... it was only the border at which height a block could be found. When it was below no block was found.

Topic: [RELEASE] Avalon Reference (Read 17869 times)