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I dont have any experience but wouldnt that mean there is hashpower going lost when it calculates things that cant be used and thrown away?
Nope; and besides, all mining algorithms work this way. 
Topic: [RELEASE] Avalon Reference - page 2. (Read 17802 times)
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How do you set the difficulty for the shares? Or is it fixed?
You don't; all core mining algorithms designed to-date work to solve difficulty 1, as do these ASICs. The controlling software is responsible for filtering out shares that don't meet the required difficulty.I dont have any experience but wouldnt that mean there is hashpower going lost when it calculates things that cant be used and thrown away?
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How do you set the difficulty for the shares? Or is it fixed?
You don't; all core mining algorithms designed to-date work to solve difficulty 1, as do these ASICs. The controlling software is responsible for filtering out shares that don't meet the required difficulty. 
This looks pretty impressive. Wish I knew what the hell I am looking at. 
Thanks for the update BitSyncom!
One critical piece seems to be missing from the chip datasheet. How do you set the difficulty for the shares? Or is it fixed?
Also, is the HDL code for the FPGA coming?
-a[g
One critical piece seems to be missing from the chip datasheet. How do you set the difficulty for the shares? Or is it fixed?
Also, is the HDL code for the FPGA coming?
-a[g
is their a way to set the fan speed at 100%?
Thanks for the update BitSyncom!
One critical piece seems to be missing from the chip datasheet. How do you set the difficulty for the shares? Or is it fixed?
Also, is the HDL code for the FPGA coming?
-a[g
One critical piece seems to be missing from the chip datasheet. How do you set the difficulty for the shares? Or is it fixed?
Also, is the HDL code for the FPGA coming?
-a[g
Looks like BitSyncom pushed a new commit that has a datasheet with some comm protocol descriptions.
EDIT: For the lazy, the new document: https://github.com/BitSyncom/avalon-ref/blob/master/SPEC/A3256Q48-130507-V03-EN.pdf
Also: https://github.com/BitSyncom/avalon-ref/blob/master/UNLICENSE
Lookin' good, team Avalon!
EDIT: For the lazy, the new document: https://github.com/BitSyncom/avalon-ref/blob/master/SPEC/A3256Q48-130507-V03-EN.pdf
Also: https://github.com/BitSyncom/avalon-ref/blob/master/UNLICENSE
Lookin' good, team Avalon!
Some people have asked about the FPGA bitstream. It makes sense that the FPGA bitstream would be one of the last things they provide in order to work out any bugs. It could be changed very last minute.
On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.
Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.
I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.
Drew
On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.
Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.
I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.
Drew
You are right.
However, they are selling bare chips. So they have some incentive to support the DIY scene too.
Yes, it's two conflicting positions, from an economic view.
It is not conflicting if they have "the greater good of bitcoin" in mind.
And from all I have seen from Avalon, I am very sure exactly that is the point.
Oh, and kudos for not wasting your time playing in the bitcointalk sandbox, Yifu. I really mean it, I much prefer you to do real work instead!
Ente
Some people have asked about the FPGA bitstream. It makes sense that the FPGA bitstream would be one of the last things they provide in order to work out any bugs. It could be changed very last minute.
On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.
Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.
I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.
Drew
On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.
Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.
I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.
Drew
How is the BOM and comms protocol coming along for release?
We really need the BOM and communication protocol and power supply current estimates...
How is the BOM and comms protocol coming along for release?
Some resistors and inductors in Control Unit circuit are undefined. What does it mean "MB" an "NC"? And which value have:
FB1
FB2
FB3
FB4
R11
R13
R23
R24
R35
R4
R5
R8
R33
R34
FB = Ferrite Bead. Its an inductor that passes DC current and blocks AC (noise) it is low resistance at DC.FB1
FB2
FB3
FB4
R11
R13
R23
R24
R35
R4
R5
R8
R33
R34
MB I don't know what this stands for but it also looks like an inductor similar to FB but could have a more inductance and resistance.
The purpose is to provide a clean DC supply free of AC noise.
NC - Could that mean not connected ? Maybe someone could look and see if the NC parts are installed.
/topic as promised.
https://github.com/BitSyncom/avalon-ref
will be updated continuously within a next few days.
https://github.com/BitSyncom/avalon-ref
will be updated continuously within a next few days.
Would you mind uploading gerber and pick&place files?
Best regards
Some resistors and inductors in Control Unit circuit are undefined. What does it mean "MB" an "NC"? And which value have:
FB1
FB2
FB3
FB4
R11
R13
R23
R24
R35
R4
R5
R8
R33
R34
/Edit because I should research before I post...FB1
FB2
FB3
FB4
R11
R13
R23
R24
R35
R4
R5
R8
R33
R34
As mentioned below by fasmax, the FB parts are probably ferrite beads for EMI suppression. In doing some research there are also small surface mount inductors used for the same purpose. These are probably what the MB parts are. If you look closely at the pictures of the control unit you can see R8 and R11 which are "MB" parts on the schematic look like what chip inductors should look like.
If someone could post a better picture of the power section on the hashing module we could probably answer this question for sure.
As for values, lets get the BOM released!
-a[g
And what exactly 2SMX and 4SMX crystals need for Control Unit board? I found nothing about it model or even frequency..
Much appreciated Yifu.
We would also appreciate it if, due to the enormously time-sensitive nature of receiving Batch #2 or Batch #3 units, you gave us some kind of option to expedite shipping. It's been >90 days since my order and I feel my brain literally melting each day that goes by.
We would also appreciate it if, due to the enormously time-sensitive nature of receiving Batch #2 or Batch #3 units, you gave us some kind of option to expedite shipping. It's been >90 days since my order and I feel my brain literally melting each day that goes by.
+1
Some resistors and inductors in Control Unit circuit are undefined. What does it mean "MB" an "NC"? And which value have:
FB1
FB2
FB3
FB4
R11
R13
R23
R24
R35
R4
R5
R8
R33
R34
FB1
FB2
FB3
FB4
R11
R13
R23
R24
R35
R4
R5
R8
R33
R34
Weird, on the hash unit, the SS34 diode is missing from the schematic (PDF).
It turns out that what Yifu released is a new revision of the hash unit PCB that does not need this diode. Most likely this is the revision that batch 2 and 3 will be built on.
@BitSynCom,
When you get a chance can you provide some supply current estimates for the 3.3V and the AVCC 1.2V reference supplies per chip? I gather that AVCC drives the clock gen circuit and you have a separate supply to keep noise minimal on that line?
Thx!
When you get a chance can you provide some supply current estimates for the 3.3V and the AVCC 1.2V reference supplies per chip? I gather that AVCC drives the clock gen circuit and you have a separate supply to keep noise minimal on that line?
Thx!
So, after looking over the design and PCB and BOM of the ASIC, it seems that all that's needed to build a clone of Avalon s units is the FPGA firmware? everything else seems to be online that's needed to the plans off to a PCB factory and get populated boards back. I doubt at an individual level the costs of building a clone would be worth it, but if someone was building a large miner why wouldn't this be a better route to go then redesigning a whole new system
BKKcoins is working or will start working on an FPGA-less firmware for an FPGA-less design of his own. Seems the better route than simply cloning.
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