Chips have zero voltage. It would be possible to set a "cut here" zone to disconnect local comms and solder pads to jump to the next node could be populated by either solder blobs or 0-ohm resistors. That's pretty much how my L-board works - except instead of "cut here" I just don't put a chip on the second pad in that node so there's nothing for it to talk to anyway. With a "cut here" you wouldn't have to worry about pulling chips, which reduces the "tools required" from a hot-air station to a $5 firestarter.
Leaving big fat pads to short around can get dangerous, because if you accidentally short them when you don't want to things could get screwed up ala Prisma. If you've got a soldering iron, knock off the node-level caps and short across their pads. Wouldn't take but a minute.
Total increase in PCB cost plus parts cost plus additional assembly, $0 - sounds like a win to me.
The chips have zero means of regulating voltage. The thing that keeps the node voltages at about 0.8V is that all the chips are operating at the same frequency and doing the same mount of work - they're all pulling the same amount of power, so the same amount of current is going through each node, so the voltage divides evenly just like it was a string of equal-value resistors. If one chip starts to misbehave, you can think of its resistance changing (either up or down depending on the error) which means the voltage across it changes and that affects how much voltage is left over to divide among the others in the string.
If you bypassed one node, you'd have to drop your board voltage by one node's worth. If you went from 15 nodes to 14 but didn't change your voltage, now your nodes get 0.860V instead of 0.800V and they start to cook a bit.
I have been wondering for a long time how the string setup worked reliably without any signs of a shunt regulator across them. So it is only because all chips are more or less doing the same operations at the same time that keeps the voltage divided evenly... Elegant solution to eliminating the need for VRM's provided all the chips have identical tested specs or apparently at least fairly close ones. Is also a dicey solution in that all must chips be doing the same operations so their loads are identical. I do hope that Bitmain is binning the chips to keep all in a chain reasonably matched!
I like your idea on adding mosfets to do just that for when a chip goes down. I assume that the bypass FET will be switched on hard for minimum losses? As you said only problem is that when a chip goes down hard ya lose coms from that point. In hardware mode, as you said - give the associated cap a push to pop it off and jumper across the pads. Perfect solution (until too many get tweaked).
Along those lines.... Looking at Bitmains spec for the S7 they call for 12vdc OR MORE. Up to 5% more.
With the s5 string setup I wonder how much neg margin we have vs stock clock speed? Bitmain had said the S5 could be fed as low as 9.7v when underclocked. On most of my rigs I usually read 12.1x at the supply and 11.92v at the PCIe connectors. The HP/IBM psu's do have a voltage trim/remote sense sooo.
Do you know how low the supplies can be set (for underclocking/volting) and how high when compensating for drop across power leads?
What pin terminal is the sense/trim input?
Btw, Schenider electric has its offices near my city, if anyone needs directions, ask away.
