Maybe someone has never raced in a formula-1 race, too...
-MarkM-
Topic: Swedish ASIC miner company kncminer.com - page 1636. (Read 3049501 times)
No intelligent company tosses $250 worth of components and PCB because a $25 chip is bad...
You do if you're in a rush to make a headline-breaking deadline, and if it's a significant number of rejects you hire someone to extract what they can off the board to put in the scrap bin.
Hypothetically if it cost them $2kUSD overhead per unit, and they sold 100,000 units expecting a 5% reject rate then they'd have 110,000 units of inventory (more in reality). Considering they're making 50% (roughly) per unit, a 1% loss per unit isn't a big deal.
No intelligent company tosses $250 worth of components and PCB because a $25 chip is bad...
Being engineers, they more than likely they ordered 30% more of everything than they needed, and they already planned for the 2nd batch orders. I would guesstimate, they have plenty of on hand and are willing to toss some components if necessary. Figure a 5% failure rate at worst for these scenarios, so it's within acceptable boundaries.
Better look at the board pricture again - because the other components on the board cost far more than the hashing chip...
There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.
If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.
This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.
You can test the chips after packaging, but before soldering it to a PCB. Soldering untested dies/chips on a PCB makes no sense to me, I cant believe thats what they will be doing.
Why not? There's only one chip per board, if it doesn't work they can just throw it out.
*patiently waiting for video and refreshing KNC website every hour*
This is called "chip level final test". They said, they won't do it. At least this is what is written in the open day Q&As report.
I know, I just assume they misunderstood the question as chip testing is like a few dollar cents per chip and pretty much always cheaper than paying for mounting and PCB.
Anyway, as you said, its their problem.
There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.
If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.
This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.
You can test the chips after packaging, but before soldering it to a PCB. Soldering untested dies/chips on a PCB makes no sense to me, I cant believe thats what they will be doing.
This is called "chip level final test". They said, they won't do it. At least this is what is written in the open day Q&As report.
There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.
If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.
This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.
You can test the chips after packaging, but before soldering it to a PCB. Soldering untested dies/chips on a PCB makes no sense to me, I cant believe thats what they will be doing.
They would be testing them individually as they were packaged. While you can't be certain of the extent of the testing unless you're involved, at the very least they're testing to sort out parts from bad dies from near the edge of the wafer (perhaps only 1 or 2 of the engines functional) and for major faults like Vcc shorted to GND.
How extensive the testing is per chip will depend on the testbeds and simulations that OrSoc provided the packager. They're doing at least gross electrical testing at a minimum. They probably are not going so far as binning parts with 4 engines showing up as functional...
How extensive the testing is per chip will depend on the testbeds and simulations that OrSoc provided the packager. They're doing at least gross electrical testing at a minimum. They probably are not going so far as binning parts with 4 engines showing up as functional...
There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.
If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.
This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.
As stated a few times, the logic of the chip was already proven before the silicon was poured. All which remains is making sure they function electrically-speaking, which doesn't take long. Mating the chips to the boards takes longer, which isn't saying much.
As to the preorder process mentioned earlier being half up front/half later, that's similar to how some preorder systems work. You pay an interest/reservation amount up front to get early buy-in, then the remainder after a certain milestone to lock your placae in. It would be nice to see more of this happening in the coin world.
As to the preorder process mentioned earlier being half up front/half later, that's similar to how some preorder systems work. You pay an interest/reservation amount up front to get early buy-in, then the remainder after a certain milestone to lock your placae in. It would be nice to see more of this happening in the coin world.
They will need to have atleast few chips to test the chip itself. They must get a lot data from the actual chip - how can they ship a product to end-user that includes a chip that has only been simulated?
If they don't have chips to test yet, they will be late. Just like Bitfurys chip differed from the simulations kinda lot. Same with BFL. How would it be different with KNC? Really?
If they don't have chips to test yet, they will be late. Just like Bitfurys chip differed from the simulations kinda lot. Same with BFL. How would it be different with KNC? Really?
They can test the chips at this point if they want too. They would know if there was a problem by now.
all your figures are wrong.
damn you were fast with your quote. 
I fixed my post in less than 2minutes. The picture KNC posted looks like a partially assembled (or maybe a completely assembled?) chip, does it not? I see orientation marks on the other four cores, which each appear to have 100 or so of those round things on them. What are those round marks, a solder connection point or something?
they are solder balls. AFAICT, the picture floating around isnt a packaged chip yet, its a cut naked die that has been bumped (surface pads and flip chip solder balls added).
Next step is mounting that to a substrate, reflowing, adding underfill etc. Only then do you have what is generally called a "chip".
Here is a picture:
more info:
http://en.wikipedia.org/wiki/Flip_chip
[funny pic]
I dont think anyone sane questioned there would be chips, not after reading the press release by orsoc.
The last months this thread was FULL of trolls questioning that there will be chips. Sane or not it doesnt matter cause we all have seen it happen.
And even now they could state that its all a photoshop fake.
You see an idiot stays an idiot regardless what happens.
KnC wasn't the only target of scam accusation, I seem to remember an unwarranted plethora of abuse directed at myself relentlessly these last few months.
Apparently not only was I talking the truth, I knew the subject I was talking about, and really did have everyone's best interests at heart with respect to secured payments, and not being scammed.
I've also been correct with every single prediction i've made. Not bad to be fair, is it?
There's a few folks here that owe me an apology, and albeit even fewer that said they would have the balls to apologise when the time came. Well let's hear it please, i'm happy to forgive, but credit, where credit's due...
heh..I was banned from BFL for pointing out that knc is taking cc direct and also that bfl was sending out disputed miner chargeback attempts with units rather then chargebacks....ie josh said that "mistake" has been fixed...and is not related to disputes heh ..so yeah I feel for you .....I may be misguided..but its hard for folks to accept stuff sometimes.......keep fighting the good fight Searing
Using ultrasonic soldering, assembly of flip-chip packages can hit 20,000 per hour. 20K chips hardly warms up the machines - it's a very short order to be running...
The picture KNC posted looks like a partially assembled (or maybe a completely assembled?) chip, does it not? I see orientation marks on the other four cores, which each appear to have 100 or so of those round things on them. What are those round marks, a solder connection point or something?
Ignored. Asshat who thinks he's a know-it-all. Joins such illustrious members on that ignore list as Kuroth, Vigil, Eve, bbxx, and atomichaos....
+1
ignored, asshat!
Yeah great to be on cirkle jerks ignore list.
I am glad i sold my knc miner shares with profit though.
[funny pic]
I dont think anyone sane questioned there would be chips, not after reading the press release by orsoc.
The last months this thread was FULL of trolls questioning that there will be chips. Sane or not it doesnt matter cause we all have seen it happen.
And even now they could state that its all a photoshop fake.
You see an idiot stays an idiot regardless what happens.
KnC wasn't the only target of scam accusation, I seem to remember an unwarranted plethora of abuse directed at myself relentlessly these last few months.
Apparently not only was I talking the truth, I knew the subject I was talking about, and really did have everyone's best interests at heart with respect to secured payments, and not being scammed.
I've also been correct with every single prediction i've made. Not bad to be fair, is it?
There's a few folks here that owe me an apology, and albeit even fewer that said they would have the balls to apologise when the time came. Well let's hear it please, i'm happy to forgive, but credit, where credit's due...
'Orama for president??
j/k......but as someone said, ORSOC was the key to all this and bitcoinorama YES you helped with all the info provided in regards to KNC. I for one will show my appreciation through a small bitcoin donation to bitcoinorama when my saturn starts cranking....looks like we are almost there.
COME ON KNC!
Using ultrasonic soldering, assembly of flip-chip packages can hit 20,000 per hour. 20K chips hardly warms up the machines...
Is there a video of this process?
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