Topic: Swedish ASIC miner company kncminer.com - page 1895. (Read 3050071 times)
Isn't bitfury's foundry UMC?
All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.
At least for STM the above statememnt isn't true. And it wasn't true for almost a year.Well, since the helveticoin user is tight lipped I had to search the STmicro press releases:
http://www.st.com/web/en/press/en/t3343
http://www.st.com/web/en/press/en/t3370
Pretty soon anyone in EU-landia could probably order this process through Europractice, the same way as bitfury did.
Quote from: October 18th 2012
Semiconductor technology leaders ST, Soitec and CMP help universities, research labs and companies prototype next generation of Systems-on-Chip
The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.
The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.
http://www.st.com/web/en/press/en/t3343
Quote from: December 11th 2012
Silicon-verified process technology delivers 30% higher speed and up to 50% improvement in power
Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, are confirming expectations and demonstrating the great flexibility of the technology and the extended voltage range exploitable through DVFS (Dynamic Voltage and Frequency Scaling).
Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, are confirming expectations and demonstrating the great flexibility of the technology and the extended voltage range exploitable through DVFS (Dynamic Voltage and Frequency Scaling).
http://www.st.com/web/en/press/en/t3370
Pretty soon anyone in EU-landia could probably order this process through Europractice, the same way as bitfury did.
CMP offers access to STMs Multi-Project-Wafer runs for SMEs and academia (comparable to Europractice). STM is probably happy about some money coming from this source to finance the MPW mask costs, because they have not enough own content. MPWs are for prototyping runs only. They are not suitable for volume production.
I'm not sure if STM will do a full-mask (not MPW) tape-out for everybody too. For customers ordering 1000 wafers of course, but for one who orders only 50?
Anyway, from the definition STM is an IDM (Integrated Device Manufacturer) not an "pure play" foundry without own chip products. Did you know that STM is a big customer of GF? The FDSOI technology mentioned above will finally also run in Dresden at the GF fab 1 (under STM licence) for volume production.
All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.
At least for STM the above statememnt isn't true. And it wasn't true for almost a year.Well, since the helveticoin user is tight lipped I had to search the STmicro press releases:
http://www.st.com/web/en/press/en/t3343
http://www.st.com/web/en/press/en/t3370
Pretty soon anyone in EU-landia could probably order this process through Europractice, the same way as bitfury did.
Quote from: October 18th 2012
Semiconductor technology leaders ST, Soitec and CMP help universities, research labs and companies prototype next generation of Systems-on-Chip
The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.
The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.
http://www.st.com/web/en/press/en/t3343
Quote from: December 11th 2012
Silicon-verified process technology delivers 30% higher speed and up to 50% improvement in power
Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, are confirming expectations and demonstrating the great flexibility of the technology and the extended voltage range exploitable through DVFS (Dynamic Voltage and Frequency Scaling).
Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, are confirming expectations and demonstrating the great flexibility of the technology and the extended voltage range exploitable through DVFS (Dynamic Voltage and Frequency Scaling).
http://www.st.com/web/en/press/en/t3370
Pretty soon anyone in EU-landia could probably order this process through Europractice, the same way as bitfury did.
CMP offers access to STMs Multi-Project-Wafer runs for SMEs and academia. STM is probably happy about some money coming from this source to finance the MPW mask costs, because they have not enough own content. MPWs are for prototyping runs only. They are not suitable for volume production.
I'm not sure if STM will do a full-mask (not MPW) tape-out for everybody too. For customers ordering 1000 wafers of course, but for one who orders only 50?
Anyway, from the definition STM is an IDM (Integrated Device Manufacturer) not an "pure play" foundry without own chip products. Did you know that STM is a big customer of GF? The FDSOI technology mentioned above will finally also run in Dresden at the GF fab 1 (under STM licence) for volume production.
Also, don't forget they promised a September delivery, NOT a 1st of September delivery. That's 4 weeks to play with.
thank you for bringing this up. so many people cant seem to comprehend this.
$800k for a 28nm full-mask set? This is an amazing offer, at which foundry will I get it that cheap?
That I do not believe KnC is producing a fully designed asic should be obvious by now.
That only works if the foundry is convinced that you are worthy of credit. Normally this is not the case for start-ups and SMEs in this price category. For them it is cash in advance or no tape-out. Yes, I know what I'm talking about, it's hard to deal directly with companies like GF or TSMC if your are only a small customer.
I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH). 1000 wafers a year would be a big customer. Why should a foundry take any risk for a bitcoin mining ASIC?
So I think they most likely have to pay the complete $1.5M to $2M in advance of the tape-out. And because they said tape-out done "some time ago", they probably paid it also some time ago.
From the commercial point of view I see no reason why KnC should not be able to produce a fully designed 28nm ASIC. They collected enough money by pre-orders to pay the complete 3rd party NREs in advance. But it should be clear, that if they are on track as they claimed, a great deal of the pre-order money isn't in their hands any more.
4. My guess, which people have posted that it is not true, is they are going with eAsic.
Yes, I'm not that far away, but do not agree with all of your points:
1. OrSOC and KnC need a channel partner of one of the two 28nm foundries to get access at all. eASIC would be a choice (also for a standard cell ASIC!), eSilicon or GUC are others. There are many and they love to take your money for that kind of projects. In this way there is no background check by the foundry required.
2. From my own experience I know that not all 28nm "giga" fabs running currently at there capacity limit. If you bring the money (as cash in advance
) through an accepted channel partner they will do a tape-out for you. They will for sure make you not the best price for masks and wafers, but they will do it, just to get workload for their fabs.3. Physical implementation and sign-off of a >100mm2 28nm die in about 6 weeks (because mid of June they didn't even have the foundry finally selected and they did tape-out "some time ago") is really a challenge, but not completely impossible. The related risk to fail for such a turbo implementation is huge. I hope they had a really experienced layout team for this job, which already did some tape-out in the concrete 28nm node.
eASIC is GF, Europe.
Altera (my guess) is TSMC, Taiwan, Asia.
ORSoC has a working relationship with both, both do standard cell and take the RTL code. I guess they just had to find the right balance between cost and delivery time. Since Asia won, that very much means they didn't choose eASIC. And they're not dealing with the foundry directly either (hoping they wouldn't take the risk of dealing with a non established partner which would really risk screwing up their timetable).
Also, don't forget they promised a September delivery, NOT a 1st of September delivery. That's 4 weeks to play with.
All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.
At least for STM the above statememnt isn't true. And it wasn't true for almost a year.Well, since the helveticoin user is tight lipped I had to search the STmicro press releases:
http://www.st.com/web/en/press/en/t3343
http://www.st.com/web/en/press/en/t3370
Pretty soon anyone in EU-landia could probably order this process through Europractice, the same way as bitfury did.
Quote from: October 18th 2012
Semiconductor technology leaders ST, Soitec and CMP help universities, research labs and companies prototype next generation of Systems-on-Chip
The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.
The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.
http://www.st.com/web/en/press/en/t3343
Quote from: December 11th 2012
Silicon-verified process technology delivers 30% higher speed and up to 50% improvement in power
Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, are confirming expectations and demonstrating the great flexibility of the technology and the extended voltage range exploitable through DVFS (Dynamic Voltage and Frequency Scaling).
Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, are confirming expectations and demonstrating the great flexibility of the technology and the extended voltage range exploitable through DVFS (Dynamic Voltage and Frequency Scaling).
http://www.st.com/web/en/press/en/t3370
Pretty soon anyone in EU-landia could probably order this process through Europractice, the same way as bitfury did.
Could the kids please go and play in the garden, while the adults are trying to have a conversation on topic.
I'm not 13 
you muts trying harder, you know start with my mom and dad bla bla bla oh sry they are death, kido 
you muts trying harder, you know start with my mom and dad bla bla bla oh sry they are death, kido ok. ignored.
I'm not 13 you muts trying harder, you know start with my mom and dad bla bla bla oh sry they are death, kido
you muts trying harder, you know start with my mom and dad bla bla bla oh sry they are death, kido $800k for a 28nm full-mask set? This is an amazing offer, at which foundry will I get it that cheap?
That I do not believe KnC is producing a fully designed asic should be obvious by now.
That only works if the foundry is convinced that you are worthy of credit. Normally this is not the case for start-ups and SMEs in this price category. For them it is cash in advance or no tape-out. Yes, I know what I'm talking about, it's hard to deal directly with companies like GF or TSMC if your are only a small customer.
I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH). 1000 wafers a year would be a big customer. Why should a foundry take any risk for a bitcoin mining ASIC?
So I think they most likely have to pay the complete $1.5M to $2M in advance of the tape-out. And because they said tape-out done "some time ago", they probably paid it also some time ago.
From the commercial point of view I see no reason why KnC should not be able to produce a fully designed 28nm ASIC. They collected enough money by pre-orders to pay the complete 3rd party NREs in advance. But it should be clear, that if they are on track as they claimed, a great deal of the pre-order money isn't in their hands any more.
4. My guess, which people have posted that it is not true, is they are going with eAsic.
Yes, I'm not that far away, but do not agree with all of your points:
1. OrSOC and KnC need a channel partner of one of the two 28nm foundries to get access at all. eASIC would be a choice (also for a standard cell ASIC!), eSilicon or GUC are others. There are many and they love to take your money for that kind of projects. In this way there is no background check by the foundry required.
2. From my own experience I know that not all 28nm "giga" fabs running currently at their capacity limit. If you bring the money (as cash in advance
) through an accepted channel partner they will do a tape-out for you. They will for sure make you not the best price for masks and wafers, but they will do it, just to get workload for their fabs.3. Physical implementation and sign-off of a >100mm2 28nm die in about 6 weeks (because mid of June they didn't even have the foundry finally selected and they did tape-out "some time ago") is really a challenge, but not completely impossible. The related risk to fail for such a turbo implementation is huge. I hope they had a really experienced layout team for this job, which already did some tape-outs in the selected 28nm node.
The 28mm chips from ORSOC is just a fantasy... a words from guy who work there...
ok christina. lol.
don't be an idiot Sir. You got a @ contacts, ask them self, or are you scare?i dont even understand what you're saying. www.rosettastone.com
The 28mm chips from ORSOC is just a fantasy... a words from guy who work there...
ok christina. lol.
don't be an idiot Sir. You got a @ contacts, ask them self, or are you scare? The 28mm chips from ORSOC is just a fantasy... a words from guy who work there...
ok christina. lol.
The 28mm chips from ORSOC is just a fantasy... a words from guy who work there...
$800k for a 28nm full-mask set? This is an amazing offer, at which foundry will I get it that cheap?
That I do not believe KnC is producing a fully designed asic should be obvious by now.
That only works if the foundry is convinced that you are worthy of credit. Normally this is not the case for start-ups and SMEs in this price category. For them it is cash in advance or no tape-out. Yes, I know what I'm talking about, it's hard to deal directly with companies like GF or TSMC if your are only a small customer.
I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH). 1000 wafers a year would be a big customer. Why should a foundry take any risk for a bitcoin mining ASIC?
So I think they most likely have to pay the complete $1.5M to $2M in advance of the tape-out. And because they said tape-out done "some time ago", they probably paid it also some time ago.
From the commercial point of view I see no reason why KnC should not be able to produce a fully designed 28nm ASIC. They collected enough money by pre-orders to pay the complete 3rd party NREs in advance. But it should be clear, that if they are on track as they claimed, a great deal of the pre-order money isn't in their hands any more.
4. My guess, which people have posted that it is not true, is they are going with eAsic.
I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).
3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.
Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?
Thanks!
KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).
I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.
Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.
This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.
An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).
For 50 wafer:
583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH
Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.
+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...
Would they need a 55mmx55mm package for a 11mmx11mm chip??
They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.
Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.
Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate?
120 mm2 in 28nm is really really huge, but can be produced. Approximately 4 dies per reticle. A nightmare were for sure the toplevel layout implementation and power sign-off.
They will have for sure yield issues, but if they integrated suitable redundancy features it should be handleable.
With respect to design complexity the related BIST (built and self test) and redundancy logic, will be as complex as the pure miner logic
. I hope they verified that right, because this was probably not part of their FPGA prototype.EDITED: To your original question. I'm pretty sure, that if the KNC die is bigger than 120 mm2 they did not a good layout implementation job. This is the minimum target that they must reach to take full advantage of 28nm (better smaller).
Aren't they already in problem land wrt the heat issue for such a small die? Won't having it smaller be worse actually? (wrt heat dissipation)
In principle you are right, but why waste all this expensive 28nm area? If you want to take full advantage of the technology scaling, you have to get as small as possible to be cost competitive. Otherwise you could also go for a 40nm implementation which would have half of the NRE costs of 28nm.
Forgot to mention, the nice effect is that power consumption scales with area, because you will have on-die shorter wires to connect the logic cells, which means less capacitance load in case of switching.
I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).
3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.
Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?
Thanks!
KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).
I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.
Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.
This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.
An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).
For 50 wafer:
583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH
Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.
+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...
Would they need a 55mmx55mm package for a 11mmx11mm chip??
They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.
Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.
Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate?
120 mm2 in 28nm is really really huge, but can be produced. Approximately 4 dies per reticle. A nightmare were for sure the toplevel layout implementation and power sign-off.
They will have for sure yield issues, but if they integrated suitable redundancy features it should be handleable.
With respect to design complexity the related BIST (built and self test) and redundancy logic, will be as complex as the pure miner logic
. I hope they verified that right, because this was probably not part of their FPGA prototype.EDITED: To your original question. I'm pretty sure, that if the KNC die is bigger than 120 mm2 they did not a good layout implementation job. This is the minimum target that they must reach to take full advantage of 28nm (better smaller).
Aren't they already in problem land wrt the heat issue for such a small die? Won't having it smaller be worse actually? (wrt heat dissipation)
...
Yeah, I did not mean Altera is a fab. They were probably just trying to decide between Altera and eASIC (unless you know of a 3rd company they have a contract with for 28nm?).
...
There is only a handful "pure play" foundries offering advanced nodes (< 65nm) in principle open for every customer. There are only 2 currently offering 28nm their own fabs: TSMC and GLOBALFOUNDRIES.
All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.
sorry for bothering but let me try to understand, do you mean that Altera usual partner is TSMC while eASIC's is GF ?
Correct.
I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).
3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.
Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?
Thanks!
KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).
I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.
Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.
This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.
An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).
For 50 wafer:
583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH
Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.
+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...
Would they need a 55mmx55mm package for a 11mmx11mm chip??
They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.
Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.
Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate?
120 mm2 in 28nm is really really huge, but can be produced. Approximately 4 dies per reticle. A nightmare were for sure the toplevel layout implementation and power sign-off.
They will have for sure yield issues, but if they integrated suitable redundancy features it should be handleable.
With respect to design complexity the related BIST (built in self test) and redundancy logic, will be as complex as the pure miner logic
. I hope they verified that right, because this was probably not part of their FPGA prototype.EDITED: To your original question. I'm pretty sure, that if the KNC die is bigger than 120 mm2 they did not a good layout implementation job. This is the minimum target that they must reach to take full advantage of 28nm (better smaller).
...
Yeah, I did not mean Altera is a fab. They were probably just trying to decide between Altera and eASIC (unless you know of a 3rd company they have a contract with for 28nm?).
...
There is only a handful "pure play" foundries offering advanced nodes (< 65nm) in principle open for every customer. There are only 2 currently offering 28nm their own fabs: TSMC and GLOBALFOUNDRIES.
All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.
sorry for bothering but let me try to understand, do you mean that Altera usual partner is TSMC while eASIC's is GF ?
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