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Topic: 1GH/s, 20w, $500 — Butterflylabs, is it a scam? - page 20. (Read 123109 times)

donator
Activity: 1218
Merit: 1079
Gerald Davis
Thats highly unlikely. Altera's documentation for Hardcopy suggests powersavings, die space (cost) savings and speed increases that are (very) far beyond a die shrink.  My guess is BFL's product isnt even on a leading edge process, but something cheaper like 90nm. An FPGA just cant be competitive with a s-asic.

Die size matters a lot.  Nobody even sells 90nm sASICs because they are so woefully inadequate compared to FPGA.  Not sure where you get this idea that they are magnitudes cheaper or higher performance.
hero member
Activity: 686
Merit: 564
Can you try and make some pictures in macro mode that makes the print on the asics readable? Im curious to find out what they are, even though its probably mundane like IO and USB. Id just like to confirm there are no custom asics on there other than what is perhaps under those heatsinks (still standing by my structured asic guess).
The ones that are readable are an AVR32 32UC3A1128 microcontroller ("128KB flash, 32KB SRAM, 10/100 ethernet MAC, full-speed (12 Mbps) USB 2.0 with embedded host capability, I2S, and a built-in audio D/A converter") and an FTDI FT2232H high-speed (480 Mbps) dual USB-to-serial converter. This thing looks to be seriously overdesigned! If they'd just added a cheap Ethernet PHY and port, it would have more than enough processing grunt to connect directly to a pool by itself and mine standalone with no computer.
hero member
Activity: 518
Merit: 500
Sigh.. dude, we know you dont believe it. Please spare us your tiresome, repetitive, content-less "cheer-leading" and use your time more productive by looking up some recipes.



I have a strong hunch you may need it.
hero member
Activity: 518
Merit: 500
So 25 passed. So does 26 in a couple of hours. No magical uncorn. Just as I predicted. BFL = great ride on the failrumorcopter. Better file those chargebacks before the time runs out. Shipping in 4-8 weeks for a while now Tongue

No test. No live demo. No announcement. No data on chips. Yeah, sounds like a typical scam to me. Has the big announcement on the 25 passed and I did not see it ? Am I just dumb ? Or, are they strong with the scam, these ones ?
hero member
Activity: 518
Merit: 500
But 28nm FPGAs arriving in Q1 will beat 40nm Hardcopy

Thats highly unlikely. Altera's documentation for Hardcopy suggests powersavings, die space (cost) savings and speed increases that are (very) far beyond a die shrink.  My guess is BFL's product isnt even on a leading edge process, but something cheaper like 90nm. An FPGA just cant be competitive with a s-asic.
legendary
Activity: 1022
Merit: 1000
BitMinter
When's the next meet ?
rph
full member
Activity: 176
Merit: 100
If this is based on something like a 40nm hardcopy III, performance and power figures look like they're in the right ballpark.

I'd agree and if this exists at all - hardcopy is the most likely explanation. But 28nm FPGAs arriving in
Q1 will beat 40nm Hardcopy w/o the massive upfront investment and loss of flexibility, so I am continuing to
invest in FPGA-based HW.

-rph

sr. member
Activity: 406
Merit: 257
Nope, hardcopy is a "real" sASIC, I think you're thinking of xilinx easypath (which is pretty much maskROM programmed FPGA).
And I never quite said that sASIC isn't competitive, I said the specific device I used was barely competitive with 45nm FPGAs. Mainly thanks to having no dedicated adder resources and being older (but also low up-front cost) technology.
If this is based on something like a 40nm hardcopy III, performance and power figures look like they're in the right ballpark.
rph
full member
Activity: 176
Merit: 100
Are you saying that sASIC like Altera Hardcopy is not used in this device ? What is used if not this chip ? Maybe you know something we don't.

Altera Hardcopy is not a structured ASIC technology, at least not in the same sense as eASIC/etc. It's an FPGA cost-down technology.
You can't repurpose the chip for MD5, DES, WEP, NTLM, etc and IMO the loss of flexibility is too large for the per-chip cost savings.

-rph
hero member
Activity: 518
Merit: 500
sASIC is not attractive for mining as it does not have the dedicated adder resources
required to compete with modern FPGAs. I think even ArtForz (who actually built an sASIC)
would agree on this point today, with the recent FPGA design optimizations.

BFL needs to show that:

a) The device can generate real, accepted shares for deepbit or another large,
respected pool at the stated power and performance level, reliably, on a long term basis

b) The device can be built in moderate volume for significantly less than $500
(or $700 or whatever they're charging now)

c) The device will ship in production in <4 weeks, regardless of how many orders they get.

-rph


I think all the FPGA producers like you are getting a bit scared. If this was real you would all be out of business as quick as a fiddle.

Are you saying that sASIC like Altera Hardcopy is not used in this device ? What is used if not this chip ? Maybe you know something we don't.
rph
full member
Activity: 176
Merit: 100
sASIC is not attractive for mining as it does not have the dedicated adder resources
required to compete with modern FPGAs. I think even ArtForz (who actually built an sASIC)
would agree on this point today, with the recent FPGA design optimizations.

BFL needs to show that:

a) The device can generate real, accepted shares for deepbit or another large,
respected pool at the stated power and performance level, reliably, on a long term basis

b) The device can be built in moderate volume for significantly less than $500
(or $700 or whatever they're charging now)

c) The device will ship in production in <4 weeks, regardless of how many orders they get.

-rph
hero member
Activity: 699
Merit: 500
Your Minion
Where's the pudd/ I mean proof.
hero member
Activity: 518
Merit: 500
Dying here for some proof. There is a slight chance this might be real after all. Thank you D&T for explaining how this could work.
rjk
sr. member
Activity: 448
Merit: 250
1ngldh
...but kinda scary doing it on a $500 board...

My point exactly  Grin

The freezer trick sounds like it ought to work too.
donator
Activity: 1218
Merit: 1079
Gerald Davis
For future reference, what is the best method to use for removing heatsinks that have been attached with thermal glue (instead of using thermal grease and holding them on with screws)?

Remove the screws (obviously).  Then twist 90 degrees.  That should break enough of the adhesion to allow you to remove the heatsink. If the heatsink isn't significantly loser you likely will need to try again.  I have done it plenty of times on things like northbridge heatsinks but kinda scary doing it on a $500 board.

NEVER pull hard straight upward.  Until you break the adhesion you have a good chance of ripping the solder joints right from the board.
hero member
Activity: 518
Merit: 500
For future reference, what is the best method to use for removing heatsinks that have been attached with thermal glue (instead of using thermal grease and holding them on with screws)?

Put them in the freezer for a few hours (in a sealed bag). They will come right off.
hero member
Activity: 518
Merit: 500
Well open FPGA miner  has the worst performance of all the bitstreams.  Also it is optimized for 150K LUTs.  Just dumping it on a larger chip wouldn't get you very good performance per mm of die space.  It would be very inefficient. 

I have no idea about the FGPA miner apps out there, but Ill take your word for it. That said, it might actually be a good idea to make much smaller chips than X6500s and the like. Particularly if you can cram 8 or more on a board.

Quote
What about it would be low risk? 

The fact that you are guaranteed to get a working chip and in relatively short time and with very little possible surprises when it comes to bugs, performance, power consumption, yields etc. All of that is very much unlike full custom designs. As for convincing VCs; they may not even care what a bitcoin is, all you need to convince them off is that there is a sizable market for energy efficient SHA2 hashing and you have a product that will outperform the established competition by triple digit numbers.

Quote
Of course there is always the risk someone else releases an even more optimized design (possibly on a larger run) and the value of your unsold chips plummet.

True that. Still, turnaround times Altera promises make this an extremely manageable risk compared to most semicon projects.  I also think the market is big enough for 2 or more players. IMO the real victims of a fierce competition here will be miners getting stuck with one generation after another of devices that are no longer profitable.
rjk
sr. member
Activity: 448
Merit: 250
1ngldh
For future reference, what is the best method to use for removing heatsinks that have been attached with thermal glue (instead of using thermal grease and holding them on with screws)?
donator
Activity: 1218
Merit: 1079
Gerald Davis
SO then should we understand or assume that this is what BFL did and they use 2 Hardcopy chips from Altera or did they do something else ?

I though we were getting custom BTC ASICs like in a couple of years not right now. Maybe Altera is not a real ASIC and just one that is generic but was customised for mining ?

Assuming this is real we won't know for sure until someone buys one and removes the heatsinks.

Still the theory isn't that these aren't custom ASICS but instead are structured ASICS (sASICS).  

A structured ASIC is partially "pre-built" with a large number of LUTs.  Very similar to an FPGA.  However in a FPGA all the routing of every possible combnation between LUTs are part of the chip.  This adds a lot of overhead.  In a sASIC there is no routing in the chip.  It is "incomplete".  

The only part that is customized in a sASIC is the routing.  A mask is built for the routing traces and a routing layer etched.  This layer is then sandwhiched w/ the "pre-built" logic layers.  Essentially is a step between a custom ASIC and an FPGA.  Since only one layer is customized it has a cheaper upfront cost than a custom ASIC (hundreds of thousands vs millions of dollars) and since it has no pre-built routing (for every possible combinatio between LUTs) it has a lower per-unit cost than an FPGA, and higher performance.

So
Custom ASIC - highest upfront cost, lowest cost per chip, higher performance per chip.
Structured ASIC - medium upfront cost, medium cost per chip, medium performance per chip.
FPGA - no/low upfront cost, highest cost per chip, lowest performance per chip.
hero member
Activity: 518
Merit: 500
SO then should we understand or assume that this is what BFL did and they use 2 Hardcopy chips from Altera or did they do something else ?

I though we were getting custom BTC ASICs like in a couple of years not right now. Maybe Altera is not a real ASIC and just one that is generic but was customised for mining ?
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