Topic: ActiveMining Overview and Speculation Thread - page 88. (Read 168030 times)
I actually dont even have the graph turned on because it is slow loading in my browser and just looking at the trade histories tells you much more... though a bit slower to assimlate, it is more detailed an accurate...
How short-sighted are these people selling at .0021? I picked up a few thousand more shares but I'm about as all-in on this venture as I'm going to get.
When there's only good news coming out, but the price still drops it's not short-shortsightedness, it's plain market manipulation that creates some panic selling.
See those huge "sell blocks" on BitFunder? It's just someone selling to himself, so that no shares/bitcoin change hands but it induces selling from others. There were no 25k+ bids to be filled in the first place, someone just created them and immediately sold shares to itself.
When unexperienced investors look at the big red volume bars they just panic.
How short-sighted are these people selling at .0021? I picked up a few thousand more shares but I'm about as all-in on this venture as I'm going to get.
It would be awesome if the USD/BTC price just rose a bit more so that Ken could shutdown the wall at the flip of a switch! 
What did this guy mean then ?
1,683,441 down from 21,000,000. Currently 20% through the wall.
He meant 1,683,441 down from 2,100,000. I think it was a typo
What did this guy mean then ?
1,683,441 down from 21,000,000. Currently 20% through the wall.
Isnt the wall suppose to be 10,000,000 total, since they keep the rest 15,000,000 shares ?
10,000,000 is the total number of shares that will be issued to shareholders, not the amount in the wall
Isnt the wall suppose to be 10,000,000 total, since they keep the rest 15,000,000 shares ?
What happens once we breach the wall? What kind of rise in share value can we expect in an x amount of time? Vague question but could someone set some less vague frames please?
Hard to say, but once the wall is breached I'd say they will double in value, as that event means ActM is effectively delivering a chip on a very quick timeframe.
What happens once we breach the wall? What kind of rise in share value can we expect in an x amount of time? Vague question but could someone set some less vague frames please?
If those shares are enough to cover the NRE costs then I could see that being a huge boost. 
1,683,441 down from 21,000,000. Currently 20% through the wall.
Thanks for the edification! Always cool to learn about the technical stuff underlying all this.
Currently it seems only KnC is going 28nm, although I can't really understand the motive for making 100GH/s chips. We are talking about machines made to run 24/7, so, not only heat is heavily concentrated (~250W in 55x55mm), if one of them breaks you lose a whole 100GH/s at the flip of a switch! You know what they say about putting all the eggs in the same basket... 
Thanks for that!
So, each Jupiter will use 4x100GH/s chips at <=1000W, each chip using a 55x55 package.
Each chip is thus 250W, so I will expect them to use a cooler the size of a graphics card, per chip.
On 250W, we can fit about 16.667 of AMC's chips (let's say 15W each), for a rated performance of 16.667x16=266.667 GH/s.
You know, like someone said, "the devil is in the details"
Ken, dhenson has already posted the link: https://www.kncminer.com/news/news-22
I have some options that expire in just over an hour and as it stands right now I don't know if I'm going to put any more money towards this project.
Please re-assure me and the other investors that your claims are genuine by posting additional evidence.
I have some options that expire in just over an hour and as it stands right now I don't know if I'm going to put any more money towards this project.
Please re-assure me and the other investors that your claims are genuine by posting additional evidence.
Thanks for that!
So, each Jupiter will use 4x100GH/s chips at <=1000W, each chip using a 55x55 package.
Each chip is thus 250W, so I will expect them to use a cooler the size of a graphics card, per chip.
On 250W, we can fit about 16.667 of AMC's chips (let's say 15W each), for a rated performance of 16.667x16=266.667 GH/s.
You know, like someone said, "the devil is in the details"
You're giving me goosebumps!
Actually this is the first I've heard of Ken writing RTL code. I'm not great with the technical side of things so a lot of your post is over my head. Can you recommend some reading to get me up to speed?
Actually this is the first I've heard of Ken writing RTL code. I'm not great with the technical side of things so a lot of your post is over my head. Can you recommend some reading to get me up to speed?
Here's an old post I did about them:
Some more information about eASIC:
"eASIC's vision and technology": https://www.youtube.com/watch?v=aQsvbvv2Dww&hd=1
"The Big eASY, eASIC Debuts 45nm FPGA Killer", a 2008 article that explains very well their eCell design, please read it attentively: http://www.eejournal.com/archives/articles/20080805_easy/
"The devices use a logic cell structure that is analogous to the LUT fabric of an FPGA, but programming is accomplished by a “configurable via” that bridges between routing metal layers. Since this is a single mask layer, there is very little cost or risk involved in programming/customizing the devices. Furthermore, in early production, the via layer can be programmed via e-beam, allowing for very small (as in 1 unit) production runs. The company can easily produce a wafer with many designs from different companies, so there is no “minimum quantity” issue for setting up the fabrication process."
"eASIC's vision and technology": https://www.youtube.com/watch?v=aQsvbvv2Dww&hd=1
"The Big eASY, eASIC Debuts 45nm FPGA Killer", a 2008 article that explains very well their eCell design, please read it attentively: http://www.eejournal.com/archives/articles/20080805_easy/
"The devices use a logic cell structure that is analogous to the LUT fabric of an FPGA, but programming is accomplished by a “configurable via” that bridges between routing metal layers. Since this is a single mask layer, there is very little cost or risk involved in programming/customizing the devices. Furthermore, in early production, the via layer can be programmed via e-beam, allowing for very small (as in 1 unit) production runs. The company can easily produce a wafer with many designs from different companies, so there is no “minimum quantity” issue for setting up the fabrication process."
ActiveMining's ace in the sleeve is the optimized RTL code (Xilinx) Ken has been developing for the last year on fpga. This is what allows for getting so many mining cores per chip (20), all processing hashes in parallel. The great thing about eASIC is that his RTL can be quickly integrated into a structured ASIC that uses their eCell division.
There are three great things about their process: (1) all their wafers are the same, for ANY kind of chip, since only the metal layer (Via4 Lithography) is customized for each project, so they can keep pumping out generic wafers to be used by all their customers, (2) since the logic layers (eCells) are generic, they can use an e-beam machine to process the metal layers in a low-volume process, even on just ONE chip, so ActM can get their hands on prototype chips very very fast and (3) they have an easicopy process that can even deliver faster, less power hungry and cheaper chips.
Bottom line: ActiveMining is just the right "guy", at the right place, at the right time. Once the NRE is paid, the game will change, and it won't be pretty to anyone that is not already developing at least a 28nm chip with similar performance/cost numbers.
Actually this is the first I've heard of Ken writing RTL code. I'm not great with the technical side of things so a lot of your post is over my head. Can you recommend some reading to get me up to speed?
At least there ActM has almost no undercutting, effectively working as a primary market.
No undercutting since BTC-TC investors bought in at .0025, while the investors at Bitfunder bought in a lot lower.
200 BTC in 20 minutes over on BTC-TC.
83,000 shares.
83,000 shares.
At least there ActM has almost no undercutting, effectively working as a primary market.
It is sad that only Havelock so far has understood why there has to be both a separate primary and secondary market.
200 BTC in 20 minutes over on BTC-TC.
83,000 shares.
83,000 shares.
Updated the original post with the shares purchased from the wall, doesn't cover 24 hours, more like 20, so I added times of when I dumped into Excel. These are for BTCT only, as far as I can tell by searching through the trade history, no shares have been purchased from that wall since 7/9 and only 800 shares fell in that day.
Vbs I read your post and it really made me think when you spoke of delays.
Typical design criteria include NRE, time to market, power consumption, performance, and unit cost. eASIC offers structured ASICs to address the problem of production times and volume. Some designers, say KNC, prefer to prototype FPGA first and then take these designs to structured ASIC, and this is where delays can come into play along with increased cost. The fab time using the straight to structured ASIC is decreased, the NRE and unit cost are of the most efficient. eASIC's Nextreme and Nextreme-2 families of structured ASICs allows Ken to design directly with these families, both of which have much shorter design times and much lower NREs
Vbs I read your post and it really made me think when you spoke of delays.
Typical design criteria include NRE, time to market, power consumption, performance, and unit cost. eASIC offers structured ASICs to address the problem of production times and volume. Some designers, say KNC, prefer to prototype FPGA first and then take these designs to structured ASIC, and this is where delays can come into play along with increased cost. The fab time using the straight to structured ASIC is decreased, the NRE and unit cost are of the most efficient. eASIC's Nextreme and Nextreme-2 families of structured ASICs allows Ken to design directly with these families, both of which have much shorter design times and much lower NREs
ActiveMining's ace in the sleeve is the optimized RTL code (Xilinx) Ken has been developing for the last year on fpga. This is what allows for getting so many mining cores per chip (20), all processing hashes in parallel. The great thing about eASIC is that his RTL can be quickly integrated into a structured ASIC that uses their eCell division.
There are three great things about their process: (1) all their wafers are the same, for ANY kind of chip, since only the metal layer (Via4 Lithography) is customized for each project, so they can keep pumping out generic wafers to be used by all their customers, (2) since the logic layers (eCells) are generic, they can use an e-beam machine to process the metal layers in a low-volume process, even on just ONE chip, so ActM can get their hands on prototype chips very very fast and (3) they have an easicopy process that can even deliver faster, less power hungry and cheaper chips.
Bottom line: ActiveMining is just the right "guy", at the right place, at the right time. Once the NRE is paid, the game will change, and it won't be pretty to anyone that is not already developing at least a 28nm chip with similar performance/cost numbers.
Another 55k purchased. 1,714,091 left. I see this picking up and turning into a frenzy the closer we get to chewing up the block.
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