Updated the original post with the shares purchased from the wall, doesn't cover 24 hours, more like 20, so I added times of when I dumped into Excel. These are for BTCT only, as far as I can tell by searching through the trade history, no shares have been purchased from that wall since 7/9 and only 800 shares fell in that day.
Vbs I read your post and it really made me think when you spoke of delays.
Typical design criteria include NRE, time to market, power consumption, performance, and unit cost. eASIC offers structured ASICs to address the problem of production times and volume. Some designers, say KNC, prefer to prototype FPGA first and then take these designs to structured ASIC, and this is where delays can come into play along with increased cost. The fab time using the straight to structured ASIC is decreased, the NRE and unit cost are of the most efficient. eASIC's Nextreme and Nextreme-2 families of structured ASICs allows Ken to design directly with these families, both of which have much shorter design times and much lower NREs
Vbs I read your post and it really made me think when you spoke of delays.
Typical design criteria include NRE, time to market, power consumption, performance, and unit cost. eASIC offers structured ASICs to address the problem of production times and volume. Some designers, say KNC, prefer to prototype FPGA first and then take these designs to structured ASIC, and this is where delays can come into play along with increased cost. The fab time using the straight to structured ASIC is decreased, the NRE and unit cost are of the most efficient. eASIC's Nextreme and Nextreme-2 families of structured ASICs allows Ken to design directly with these families, both of which have much shorter design times and much lower NREs
ActiveMining's ace in the sleeve is the optimized RTL code (Xilinx) Ken has been developing for the last year on fpga. This is what allows for getting so many mining cores per chip (20), all processing hashes in parallel. The great thing about eASIC is that his RTL can be quickly integrated into a structured ASIC that uses their eCell division.
There are three great things about their process: (1) all their wafers are the same, for ANY kind of chip, since only the metal layer (Via4 Lithography) is customized for each project, so they can keep pumping out generic wafers to be used by all their customers, (2) since the logic layers (eCells) are generic, they can use an e-beam machine to process the metal layers in a low-volume process, even on just ONE chip, so ActM can get their hands on prototype chips very very fast and (3) they have an easicopy process that can even deliver faster, less power hungry and cheaper chips.
Bottom line: ActiveMining is just the right "guy", at the right place, at the right time. Once the NRE is paid, the game will change, and it won't be pretty to anyone that is not already developing at least a 28nm chip with similar performance/cost numbers.
