Quote
.... scheduled to be released in late November or December.
late November or December. ? why so late?
Topic: ACTUAL Butterfly Labs PCB pics! - page 11. (Read 40283 times)
late November or December. ? why so late?
It looks like all of the ASIC products will be built around the same board, populated differently. This raises a question: since the ASIC in the Jalapeño is significantly underclocked to keep power consumption down, would it be feasible to add in some of the power-supply components of the other models and a heatsink to get the Jalapeño running at the full 7.5 GH/s that the chip can deliver?
a major issue is the FPGA they are using (e.g. Altera S3) is a flip-chip package. and their ASIC is low cost wire-bond QFN. this package glue the DIE to the metal GND pad at the bottom. the θJb (to board)is low but the θJt (to top) is high. so it won't work whatever you do from the top.
Yeah, that was one of the first things I noticed too. They've basically got the entire thickness of the plastic chip package insulating their die from the heatsink that's meant to be cooling it.my question is, as a ASIC developer too, i will prepare everything before our chip comes back, and will know if it work or not in a few hours test. now there are well assembled board pictures, but still no testing data.
And that's the other one. At this point I don't even believe major hardware manufacturers who show off pretty boards without bothering to mention little details like whether they actually work; NVidia famously pulled off a similar stunt, for instance.
Now if only they would post a screenshot of it actually mining...
Late November or December huh? Makes me wish I had enough BTC to hedge my bets with Tom, so no matter who delivers first, I can get in before difficulty shoots sky high.
I think it's about 30Gh for one board if they are using 65nm, or 60Gh preboard if they are using 40nm.
And i think there must be another heat sink at the backside of the board.
And i think there must be another heat sink at the backside of the board.
Would be impressive if they were using 40 nm, but I somehow doubt it. The main reason being that it means there isn't much room to grow. As a company BFL would want to have room to lower the die size in order to make 'next-gen' ASICs that can run faster, cooler, and more efficiently. Unless they are gambling on there only being 1 generation of ASICs...
other than the weird bulged out one.. they look great but do they work?
With a bulge that big I doubt it. It wouldn't mate evenly with the HeatSink.Might be a defective board they are holding in front of the camera.
other than the weird bulged out one.. they look great but do they work?
Here is a full-sized side by side wallpaper 
.
http://www.anonmgur.com/up/746d0a6ba54410ec39c8209abd266dc1.jpg
.http://www.anonmgur.com/up/746d0a6ba54410ec39c8209abd266dc1.jpg
Do my eyes decieve me, but does ASIC chip 4 (1st on second row) look like its bulged out?
POP!
Those ASICS look like a square piece of black duct tape lol
Here is a full-sized side by side wallpaper .
.Do my eyes decieve me, but does ASIC chip 4 (1st on second row) look like its bulged out?
POP!
a major issue is the FPGA they are using (e.g. Altera S3) is a flip-chip package. and their ASIC is low cost wire-bond QFN. this package glue the DIE to the metal GND pad at the bottom. the θJb (to board)is low but the θJt (to top) is high. so it won't work whatever you do from the top.
Yeah, that was one of the first things I noticed too. They've basically got the entire thickness of the plastic chip package insulating their die from the heatsink that's meant to be cooling it.my question is, as a ASIC developer too, i will prepare everything before our chip comes back, and will know if it work or not in a few hours test. now there are well assembled board pictures, but still no testing data.
And that's the other one. At this point I don't even believe major hardware manufacturers who show off pretty boards without bothering to mention little details like whether they actually work; NVidia famously pulled off a similar stunt, for instance. 
Just as a side note, the board is 92mm X 92mm.
Regards,
Nasser
... and the hand in the OP is fake right ...Regards,
Nasser
Photoshop FTW
Was it scaled correctly or is that one a little off?
The 2nd post looks real, but I think the 1st hand is a Photoshop.
Edit: the thumb shadow gives it away
Here is a full-sized side by side wallpaper .
. 
it looks nice. i like the heatpipes and copper. I see one connector for fans on the front (on bfl website) and 1 pin on the backside that may belong to another fan connector (i know they are not called "fan connector", 3pin connector? whatev). i really hope those are meant for the sc minirig, because otherwise i assume they are planned for cooling the single actively.
If not 60watt seem legit for a cooler that size. Hm..
If not 60watt seem legit for a cooler that size. Hm..
The heatsink your looking at is the one currently used on the FPGA Single (they have not updated the pic as of yet to an image of a ASIC ),which consumed 80 watts & was designed for a 72F enviroment.
But they may be able use something similar on the ASIC,just beefed up a little to allow it to operate in an environment of 90F this time.
a major issue is the FPGA they are using (e.g. Altera S3) is a flip-chip package. and their ASIC is low cost wire-bond QFN. this package glue the DIE to the metal GND pad at the bottom. the θJb (to board)is low but the θJt (to top) is high. so it won't work whatever you do from the top.
my question is, as a ASIC developer too, i will prepare everything before our chip comes back, and will know if it work or not in a few hours test. now there are well assembled board pictures, but still no testing data.
why?
To build suspense in us doe eyed fools???
Just as a side note, the board is 92mm X 92mm.
Regards,
Nasser
Regards,
Nasser
it looks nice. i like the heatpipes and copper. I see one connector for fans on the front (on bfl website) and 1 pin on the backside that may belong to another fan connector (i know they are not called "fan connector", 3pin connector? whatev). i really hope those are meant for the sc minirig, because otherwise i assume they are planned for cooling the single actively.
If not 60watt seem legit for a cooler that size. Hm..
If not 60watt seem legit for a cooler that size. Hm..
The heatsink your looking at is the one currently used on the FPGA Single (they have not updated the pic as of yet to an image of a ASIC ),which consumed 80 watts & was designed for a 72F enviroment.
But they may be able use something similar on the ASIC,just beefed up a little to allow it to operate in an environment of 90F this time.
a major issue is the FPGA they are using (e.g. Altera S3) is a flip-chip package. and their ASIC is low cost wire-bond QFN. this package glue the DIE to the metal GND pad at the bottom. the θJb (to board)is low but the θJt (to top) is high. so it won't work whatever you do from the top.
my question is, as a ASIC developer too, i will prepare everything before our chip comes back, and will know if it work or not in a few hours test. now there are well assembled board pictures, but still no testing data.
why?
I think it's about 30Gh for one board if they are using 65nm, or 60Gh preboard if they are using 40nm.
And i think there must be another heat sink at the backside of the board.
So you suppose a low nanometer product, this would agree with a low power usage, do you think their estimates to be possible?And i think there must be another heat sink at the backside of the board.
my estimates all based on their announced specifications. it's a backward induction.
it looks nice. i like the heatpipes and copper. I see one connector for fans on the front (on bfl website) and 1 pin on the backside that may belong to another fan connector (i know they are not called "fan connector", 3pin connector? whatev). i really hope those are meant for the sc minirig, because otherwise i assume they are planned for cooling the single actively.
If not 60watt seem legit for a cooler that size. Hm..
If not 60watt seem legit for a cooler that size. Hm..
The heatsink your looking at is the one currently used on the FPGA Single (they have not updated the pic as of yet to an image of a ASIC ),which consumed 80 watts & was designed for a 72F enviroment.
But they may be able use something similar on the ASIC,just beefed up a little to allow it to operate in an environment of 90F this time.
I think it's about 30Gh for one board if they are using 65nm, or 60Gh preboard if they are using 40nm.
And i think there must be another heat sink at the backside of the board.
So you suppose a low nanometer product, this would agree with a low power usage, do you think their estimates to be possible? And i think there must be another heat sink at the backside of the board.
I think it's about 30Gh for one board if they are using 65nm, or 60Gh preboard if they are using 40nm.
And i think there must be another heat sink at the backside of the board.
And i think there must be another heat sink at the backside of the board.
Jump to: