Topic: ACTUAL Butterfly Labs PCB pics! - page 8. (Read 40283 times)

Attached are some more pictures of the Jalapeno.  It's in one of it's prototype homes, but the design is changed and we are waiting on the updated box to be delivered now.  However, the fundamental design will remain unchanged, just some cosmetic changes (laser etched top, no silver, etc...)

We are not going to make the first half of November shipping goal.  Right now, I want to say fourth or fifth week of November, but lots of little issues have cropped up, pushing the shipping date out a bit here and there. To be on the safe side, I would estimate the end of November / beginning of December as a likely ship date.  We've had some trouble sourcing the VFD screens for the Minirig SC; the wharehouse told us they had about 5x as many screens as they really have on hand, so we are coming up short.  The good news is that we've come up with an alternate solution that is so full of awesome, I am going to save that for a later update. It is, however, necessitating a redesign of the Minirig SC case, though it won't really affect the timeline in any material fashion, as it's just one part that needs to be changed a bit to accommodate the new screen.

We are also still waiting on the HSF for the Single SC to show up - the factory has been a bit slow in that department, so that set things back a bit. 

We expect the final chip versions to be in our hands in ~25 days, with final assembly and shipping to begin a few days after that.

https://bitcointalksearch.org/topic/cooling-bfl-singles-100662

 

Many of the shipping FPGA Singles have a passive heatsink on the bottom already. I was just suggesting that  a similar approach could be taken (by BFL) for the SC Singles.

I use some milled copper heatsinks very similar to these (or the 1,000 others available) and like them muchly.

As for "bracing" them against the case, bad idea to create new paths to ground.  Also, more noisy badness.

If the boards are already made, and asics already placed, something like this would probably be enough:




What'd be ideal is if these were almost exactly the same height as the space between bottom of board to enclosure, so that if the thermal adhesive proves not to be reliable, at least the heatsinks will be kept in place (not a bunch of copper pieces shaking around and contacting the board).

Would it be possible to solder something like this to the board before the ASIC chips are placed?

I wonder what the ARM place holder is for ? how could an ARM chip benefit the board ?

The pics with Henrietta are taken with my 5DMk2, though I scale them down for the web of course.

We actually agonized a lot over the plastic issue and went through scenario after scenario due to specifically that fact.  There a bunch of vias on the bottom of the board, and we were originally going to cool it from the bottom instead of the top, but simulation after simulation showed it was more effective from the top, so that's what we went with.  But the vias are still there for a bit of extra oomph when the clock rate is bumped up.

There's a pic of the back of the board on the BFL forums.

It's not always easy to find something there, so the link is: the back of the board

What passive heatsink are you using on the bottom?

What passive heatsink are you using on the bottom?

It may be worthwhile putting a passive heatsink on the bottom as well to give the device more thermal headroom. Some/most/all of my FPGA Singles have this (some also have a small fan at the bottom).

It's not always easy to find something there, so the link is: the back of the board

There's a pic of the back of the board on the BFL forums.

We actually agonized a lot over the plastic issue and went through scenario after scenario due to specifically that fact.  There a bunch of vias on the bottom of the board, and we were originally going to cool it from the bottom instead of the top, but simulation after simulation showed it was more effective from the top, so that's what we went with.  But the vias are still there for a bit of extra oomph when the clock rate is bumped up.

It is the same form factor as the current FPGA Singles.

The ASICs themselves appear to have a plastic top; not the most efficient thermal interface to a top-mounted metal heatsink. Although 7W/chip isn't huge, the combination of 8 of them in close proximity generates a lot of concentrated heat. Transferring 60W from plastic chips to a metal heatsink can be a challenge.

Also, mounting a monolithic heatsink across 8 separate chips poses another challenge: if those chips are not coplanar, the contact between the heatsink and some of the chips will not be 'perfect'; the gap will be taken up by the thermal transfer compound which would further restrict thermal conductivity.

The good news is that the SC Single uses less power than the FPGA Single, which will mitigate the situation a bit. Plus, the 8 ASIC chips, though plastic, have an overall larger surface area then the 2 metal-top FPGAs in the old Singles. More surface area makes it easier to transfer heat.

So all in all I don't think cooling these will be an issue; I'm sure BFL has already thought of all this and they have plenty of experience with the FPGA Singles. The SC board is 92mmx92mm, so it seems clear from the mounting holes that BFL will continue to use a standard 92mm fan for cooling.