no interest in selling your miner or dev services?
also is that normal to have the intro pricing then jack it up, whitefire also says its $4k now but 5k + next month
It's the first time I've ever seen a company do that with FPGAs, that's for sure. Only avnet is doing it, digikey wants $5200/board for low QTY. My pricing just depends on chip order quantity, the more ordered, the lower the price is going to get.
I don't trust % fees for dev services because they're so easy to avoid paying.
Really? This is standard operating procedure for Xilinx. Dev boards are usually sold cheaper than even just the chip cost for normal quantities. They want to make it easy for people to build things around their expensive chips, but still make all the margins on chips. I too have been talking to Xilinx and trying to get them to see there is a big market here, big enough to make up for their margins on some of these chips.
There is more FPGA hardware coming pretty soon (over the next 2-3 months) from a few sources (disclosure - myself included). Generally speaking most are going to be in the same ballpark cost/performance, but there may be outliers or easier entry level costs.
The problem with FPGAs is it is very hard to protect the bitstream if you aren’t selling the hardware. You can sell hardware that will work with your encrypted bitstreams and also support unencrypted bitstreams (anyone can make new miners). You can also lock hardware to only your encrypted bitstreams. But if you don’t sell the hardware (and burn in the encryption keys) anyone can copy it. So that leaves virtuous open source, or people making profit on hardware alone. The tools and time to develop these things are very expensive, so you likely won’t find a lot of people giving it away for free. Development time is also much longer. If I make a change that actually needs tested on real hardware of VCU1525 size, expect hours for a very fast computer to synthesize and route it before I can test it. A lot can be done in simulation, but the last mile takes a lot of time.
It is possible to use normal methods to try and protect the “command and control” normal software that drives the FPGA, but someone could reverse engineer that - just like OpenCL kernels.
If you think the FPGA is magic and the OpenCL compiler will give you 10-50x performance over your GPU, you will be sorely disappointed. Those of us seeing these gains are (afaik) writing very low level RTL to do so. There’s a big difference between OpenCL and RTL for FPGAs vs OpenCL vs ISA Assembky for GPUs.