OK, that explains why it loaded so much slower on my lancelot than the original bitcoin bitstream.
Ngzhang's instructions for the Icarus (link) (scroll down a bit) specified 1 bit and I just used the same for the lancelot.
It's also worth power cycling the board and seeing if the bitstream loads anyway, since it could just be a quirk with the final initialization step.
Topic: [ANN][BLC] Blakecoin Blake-256 for GPU/FPGA With Merged Mined Pools Stable Net - page 113. (Read 409571 times)
April 08, 2014, 12:25:39 PM
April 08, 2014, 12:19:04 PM
Hi,
Was just posting re. the data width, I have selected 4 which works with Lancelot (was following instructions here: http://www.cardreaderfactory.com/lancelot-firmware-update.html?sl=en)
I will try again with 1 and see what happens.
It seems to be failing after verification so presumably at the initialisation stage.
Thanks.
Was just posting re. the data width, I have selected 4 which works with Lancelot (was following instructions here: http://www.cardreaderfactory.com/lancelot-firmware-update.html?sl=en)
I will try again with 1 and see what happens.
It seems to be failing after verification so presumably at the initialisation stage.
Thanks.
April 08, 2014, 12:13:15 PM
Working with Bluedragon's .bit file!
Great. The only problem is the need to reprogram each time you power up the board
What stage did the MCS programming fail at? There are several distinct steps, AFAIR
1. It downloads a special programming bitstream to the FPGA
2. Erasure of the ROM
3. Program the ROM
4. Verify the ROM
5. Initialize bitstream from ROM
Did you set the SPI PROM device to "W25Q64BV/CV", 1bit ?
April 08, 2014, 12:07:32 PM
Working with Bluedragon's .bit file!
Getting WU of 13.7 after 5 mins.
Getting WU of 13.7 after 5 mins.
April 08, 2014, 12:00:43 PM
Bzyzny,
I have the Icarus initialising Jtag chain successfully. I'm using 13.1 64 bit - which worked to program a Lancelot previously.
I haven't needed to reset anything on the Icarus to get this far.
However, after programming, I get an error as follows:
"Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
INFO:iMPACT - '1': Flash was not programmed successfully."
Currently stuck at this point.
Kramble,
I am using the .mcs file which you posted earlier in this thread, which works on my Lancelot board. I will try a .bit file and see if I have any more success.
I have the Icarus initialising Jtag chain successfully. I'm using 13.1 64 bit - which worked to program a Lancelot previously.
I haven't needed to reset anything on the Icarus to get this far.
However, after programming, I get an error as follows:
"Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
INFO:iMPACT - '1': Flash was not programmed successfully."
Currently stuck at this point.
Kramble,
I am using the .mcs file which you posted earlier in this thread, which works on my Lancelot board. I will try a .bit file and see if I have any more success.
April 08, 2014, 11:32:02 AM
Thanks for the info re. Lancelot WU etc. I am using 195MHz clock and Icarus Timing 1.0 = 20 so looks like it's doing OK.
Currently trying to get an Icarus working. I am using a bunch of chopped off resistor ends as a Jtag connector, will let you know if it works. I am assuming I can use the same .mcs file as for the Lancelot board.
If it's any help to the others trying to program these, the GND lines appear to be on the top row of the Jtag connector when viewed with the writing facing the correct way. This makes VREF the bottom right pin.
Currently trying to get an Icarus working. I am using a bunch of chopped off resistor ends as a Jtag connector, will let you know if it works. I am assuming I can use the same .mcs file as for the Lancelot board.
If it's any help to the others trying to program these, the GND lines appear to be on the top row of the Jtag connector when viewed with the writing facing the correct way. This makes VREF the bottom right pin.
I guess that could work, though the resulting pins might be a bit too thin. It's a bit unfortunate that the standard connector is 2mm pitch as 0.1 inch header strips are much easier to get hold of. You don't need to connect all 14 pins, just the 6 VREF,GND,TMS,TCK,TDO,TDI (see the schematic I linked in the post above).
The lancelot bitfile should work on icarus (that was the original intention), and you can easily convert the bit file to mcs using impact, the procedure is documented somewhere on the forums but just FYI these are my crib notes (the 45 minutes is for my homebrew parallel port JTAG programmer, the USB one should be a lot faster, 15 minutes ISTR from bluedragon)
Code:
Power cycled the Lancelot (so now has bitcoin bitstream)
Assigned blakefourbufce-2core-ucf146-fmax154.bit (probably unnecessary)
Double click on left-pane "Create PROM FILE (PROM File Formatter)"
Step1: SPI Flash/Configure Single FPGA and press green arrow
Step2: Select 64M / Add Storage Device and press green arrow
Step3: Browse to C:\Blakecoin and set name blakefourbufce-2core-ucf146-fmax154.MCS (paste it in)
Leave rest at defaults (Fill FF, MCS, No).
Press OK. Dialog box opens "Start adding", press OK the browse to blakefourbufce-2core-ucf146-fmax154.bit
At "Add another" press NO.
HMM, it has NOT created a MCS file!! Aha, need to do... Operations/GenerateFile
Creates MCS, PRM, CFI files (the last two are tiny)
Return to Boundary Scan tab
Right click on 1st FPGA, Add SPI/BPI, select the MCS file, SPI PROM, "W25Q64BV/CV", 1
Now we have a "FLASH" button
Repeat for 2nd FPGA
Click on the 1st FPGA FLASH, Right Click and Program, Takes approx 45 mins (Erase/Program/Readback) 46% on progress bar.
NB FPGA is in programmed state on completion.
Repeat for 2nd FPGA
Power cycled ... HMM, takes around 12 seconds to initialize, a LOT SLOWER then bitcoin did! But its OK.
Perhaps this is because I specified a 1 bit PROM (from Ngzhang on Icarus), maybe Lancelot allows more?
Tested with "./blakeminer.py 195" ... working OK on both devices (0..3 and 8..b MSB nonces).
Assigned blakefourbufce-2core-ucf146-fmax154.bit (probably unnecessary)
Double click on left-pane "Create PROM FILE (PROM File Formatter)"
Step1: SPI Flash/Configure Single FPGA and press green arrow
Step2: Select 64M / Add Storage Device and press green arrow
Step3: Browse to C:\Blakecoin and set name blakefourbufce-2core-ucf146-fmax154.MCS (paste it in)
Leave rest at defaults (Fill FF, MCS, No).
Press OK. Dialog box opens "Start adding", press OK the browse to blakefourbufce-2core-ucf146-fmax154.bit
At "Add another" press NO.
HMM, it has NOT created a MCS file!! Aha, need to do... Operations/GenerateFile
Creates MCS, PRM, CFI files (the last two are tiny)
Return to Boundary Scan tab
Right click on 1st FPGA, Add SPI/BPI, select the MCS file, SPI PROM, "W25Q64BV/CV", 1
Now we have a "FLASH" button
Repeat for 2nd FPGA
Click on the 1st FPGA FLASH, Right Click and Program, Takes approx 45 mins (Erase/Program/Readback) 46% on progress bar.
NB FPGA is in programmed state on completion.
Repeat for 2nd FPGA
Power cycled ... HMM, takes around 12 seconds to initialize, a LOT SLOWER then bitcoin did! But its OK.
Perhaps this is because I specified a 1 bit PROM (from Ngzhang on Icarus), maybe Lancelot allows more?
Tested with "./blakeminer.py 195" ... working OK on both devices (0..3 and 8..b MSB nonces).
You might want to try bluedragon's tri-core bitstream (it's on the previous page) which only clocks at 160MHz, but is around 25% faster due to the additional core.
April 08, 2014, 10:29:26 AM
Hi Kramble,
Thanks for the info re. Lancelot WU etc. I am using 195MHz clock and Icarus Timing 1.0 = 20 so looks like it's doing OK.
Currently trying to get an Icarus working. I am using a bunch of chopped off resistor ends as a Jtag connector, will let you know if it works. I am assuming I can use the same .mcs file as for the Lancelot board.
If it's any help to the others trying to program these, the GND lines appear to be on the top row of the Jtag connector when viewed with the writing facing the correct way. This makes VREF the bottom right pin.
Thanks for the info re. Lancelot WU etc. I am using 195MHz clock and Icarus Timing 1.0 = 20 so looks like it's doing OK.
Currently trying to get an Icarus working. I am using a bunch of chopped off resistor ends as a Jtag connector, will let you know if it works. I am assuming I can use the same .mcs file as for the Lancelot board.
If it's any help to the others trying to program these, the GND lines appear to be on the top row of the Jtag connector when viewed with the writing facing the correct way. This makes VREF the bottom right pin.
April 08, 2014, 05:04:48 AM
maybe they got programmed by edge connector?
Yep, the JTAG signals are brought out to the DIMM connector (page 2 of the schematic). It should be possible to check signal continuity between the JTAG cable and the edge connector pins using a multimeter (expect 200 ohm resistance due to two sets of series protection resistors, though the ESD protection diodes on the FPGA chips may confuse the issue). I'd probably do this as a last resort though, as there is no knowing what sort of voltages a random multimeter would apply to the board.
April 08, 2014, 04:52:53 AM
maybe they got programmed by edge connector? also if I remember correctly green boards are prototype and blue was production? maybe this is why they are not fully populated 
April 08, 2014, 04:25:01 AM
Ah, I didn't realize these boards did not include the JTAG connector (which also raises the question of how they were programmed in the first place? Bed of nails or factory programming of the SPI ROMs I would guess).
Bzyzny, if you soldered your own connector, then check for dry joints or shorts. It's possible one of the signal pins is open-circuit which would be consistent with the error message. Also the socket orientation, but that's less likely as it would swap VCC and GND (the entire odd row of pins is connected to ground, the even row has VCCAUX and the four signals TMS, TCK, TDO, TDI on pins 2,4,6,8,10).
The schematic is at https://github.com/ngzhang/Icarus in Downloads/SCHinPDF (you can't view it on the web, need to download the entire git as a zip file). The JTAG connector is on the first page of the PDF, at the top left.
Bzyzny, if you soldered your own connector, then check for dry joints or shorts. It's possible one of the signal pins is open-circuit which would be consistent with the error message. Also the socket orientation, but that's less likely as it would swap VCC and GND (the entire odd row of pins is connected to ground, the even row has VCCAUX and the four signals TMS, TCK, TDO, TDI on pins 2,4,6,8,10).
The schematic is at https://github.com/ngzhang/Icarus in Downloads/SCHinPDF (you can't view it on the web, need to download the entire git as a zip file). The JTAG connector is on the first page of the PDF, at the top left.
April 08, 2014, 02:29:47 AM
mogrith yes just make sure you get a 2mm 14pin header that fits your cable. if you have success please share your info since im trying to get one of these working too
I would double check the pinouts on the cable between the programmer and the board I think thats why iMPACT does not detect your chain
April 07, 2014, 11:31:34 PM
mogrith yes just make sure you get a 2mm 14pin header that fits your cable. if you have success please share your info since im trying to get one of these working too
April 07, 2014, 04:54:31 PM
Just got this in the mail. Need to get a 14 pin jtag connector?
April 07, 2014, 02:47:33 PM
Heres the log output from impact:
http://pastebin.com/f0ysKxN4
The programmer is a dlc9g, any other info you need?
http://pastebin.com/f0ysKxN4
The programmer is a dlc9g, any other info you need?
April 07, 2014, 01:18:45 PM
EU1 is one of the only pools with a fixed fee and it is very unlikely I would 51% attack my own blockchain 
EU2 is using the newer MPOS and is more stable will leave it as is for now, SF1 is still down not rebuilt it yet been working on merge mine stuff
Note: 51% is not an issue if the pool operator is trusted (I am not going to attack or double spend on my own blockchain) but it is a target for DDoS so make sure you put a failover pool in cgminer or use one of the other pools
EU2 is using the newer MPOS and is more stable will leave it as is for now, SF1 is still down not rebuilt it yet been working on merge mine stuff
Note: 51% is not an issue if the pool operator is trusted (I am not going to attack or double spend on my own blockchain) but it is a target for DDoS so make sure you put a failover pool in cgminer or use one of the other pools
April 07, 2014, 12:40:18 PM
on ny1 right now. I had problems with sf1 and just switched to ny1.
April 07, 2014, 12:32:11 PM
i noticed theres a large concentration of miners on eu1 pool. it would be good if people could spread out some, eu2 sg1 and the ocminer pool are all pretty much empty.
I bet the pool operator is preparing a 51% attack 
Just increase the mining fee and people will switch. Also I dont think we need 2 eu pools right now.
April 07, 2014, 11:30:29 AM
i get stuck at step 4, it does not show the 2 fpgas after i run initialize chain, instead it gives this error:
ERROR:iMPACT - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage.
the led on the xilinx programmer turns green when i power up the fpga. impact appears to recognize the device is there, based on the log output, but im at a loss as to what is preventing the jtag chain from initializing. I even tried doing it on a different computer (with windows 7 32bit) and a different version of ise (14.2). any steps i can take to narrow down the problem? thanks
ERROR:iMPACT - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage.
the led on the xilinx programmer turns green when i power up the fpga. impact appears to recognize the device is there, based on the log output, but im at a loss as to what is preventing the jtag chain from initializing. I even tried doing it on a different computer (with windows 7 32bit) and a different version of ise (14.2). any steps i can take to narrow down the problem? thanks
some pictures of your setup might help us spot anything that is not connected right
April 07, 2014, 05:55:51 AM
i get stuck at step 4, it does not show the 2 fpgas after i run initialize chain, instead it gives this error:
ERROR:iMPACT - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage.
the led on the xilinx programmer turns green when i power up the fpga. impact appears to recognize the device is there, based on the log output, but im at a loss as to what is preventing the jtag chain from initializing. I even tried doing it on a different computer (with windows 7 32bit) and a different version of ise (14.2). any steps i can take to narrow down the problem? thanks
ERROR:iMPACT - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage.
the led on the xilinx programmer turns green when i power up the fpga. impact appears to recognize the device is there, based on the log output, but im at a loss as to what is preventing the jtag chain from initializing. I even tried doing it on a different computer (with windows 7 32bit) and a different version of ise (14.2). any steps i can take to narrow down the problem? thanks
Could you post that part of the log, it may give some insight on the problem?
Stating the obvious, there seem to be three possibilities:
1. Faulty cabling
2. Faulty programmer (or less likely a software/driver incompatibility)
3. Faulty icarus
The icarus uses a different (14 pin) JTAG connector to the lancelot's 6 pin, but looking at the icarus schematic, it seems to have two additional 6 pin connectors (both on one side of the heatsink). Be sure that you are NOT connecting to those!! Unlikely I know, but worth putting it out there just to be sure (from the schematic, it looks like it these connectors would in fact supply the correct VCC/GND levels, so they could confuse the programmer into giving a green light!).
If you have access to another JTAG device (eg a CM1 or even some random non-mining kit), you could try connecting to that in order to rule out a faulty programmer (no need to do any programming, just check that a scan chain is detected).
April 07, 2014, 04:03:30 AM
I want to join BlueDragon in thanking you for lending some real help on the development side of things.......
Awesome this might help thanks
any other help, tips, tricks most welcome
will add that auth module to eloipool
no problemo im in #cryptopools on freenode irc if u need any help fast (theres a few other pool ops in there too).
I'd be willing to help with this as ive always been interested in getting it working. a good idea if you are good with sql is to work out the sql structure (and the configs in use) here: http://github.com/60E/php-mpos
About the worker auth, i have a module in my repo which will get eloipool to use the database to authorise users. Eloipool will also likely need the db query modified to work efficiently with MPOS or you will run into a lot of cron errors (i ran eloipool before i began work on stratum)
About the worker auth, i have a module in my repo which will get eloipool to use the database to authorise users. Eloipool will also likely need the db query modified to work efficiently with MPOS or you will run into a lot of cron errors (i ran eloipool before i began work on stratum)
Awesome this might help thanks
any other help, tips, tricks most welcome
will add that auth module to eloipool
no problemo im in #cryptopools on freenode irc if u need any help fast (theres a few other pool ops in there too).
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