It must be common knowledge that the Ztex FPGA frequency adjustment is not perfect, but here's another anecdote. I recently got an original 1.15y board where two of the chips are impossible to run without forced clock limits. Basically, they start giving lots of HW errors at 188 or 192 MHz, and they end up SICK. After setting an upper limit of 184, they run fine, with zero HW errors. It's as if the HW vs. frequency is an extremely steep function for these chips.
The board runs SHA-2 code fine at nearly 220 MHz, though the two chips are the slowest of the bunch. I also have other 1.15y/x boards where Blake runs fine with the default adjustment on cgminer 3.1.1
To answer a question in the README,
I don't know if this will work for multiple boards
I got the freq limits working for two boards using
--ztex-clock 180:184,180:248,180:248,180:184,200:248,200:248,200:248,200:248
All in all, this is not a bug report or anything, but an interesting finding. I've tried both of the currently available bitstreams with similar results.