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Topic: BFL ready to ship? (Read 10386 times)

RHA
sr. member
Activity: 392
Merit: 250
March 11, 2013, 02:55:38 PM
#90
- they surely use mostly the edge pins of the chip (because of quick QFN to FCBGA conversion), leaving  most of the middle pins unused;
1) This is simply wrong.  When converting from QFN to FCBGA, the upper layer of metal on the silicon is changed to a miniature version of the BGA package.  Proof of this is the photos of the wire bonding test die.  The attachment points are (now) in an array, not along the edge.  Note that the die can have typically more or sometimes less connections than the final BGA package.  The BGA package is simply a very tiny multi-layer PCB that translates the chip balls/bumps to the package ball grid on the bottom.
I wrote this just because of where the wires went on the photo of test die. Mostly the edge pins, most of the middle pins were left unused, so I concluded they have done it to avoid big changes of their PCB (miner's one, not BGA's one).
But I agree - it could be because of difficulty of wiring the middle pins.
sr. member
Activity: 310
Merit: 250
March 11, 2013, 02:45:26 PM
#89
For reference...

http://imgur.com/sicFhlY

not very even at all, but better than the BFL chips... and those chips aren't clocking as high as this Athlon did.

Conclusion: We're going to have to wait and see.
legendary
Activity: 1400
Merit: 1005
March 11, 2013, 01:23:30 PM
#88
Good god



What, they didn't apply the glue that holds the metal caps in place evenly?
 Huh
That's what I was thinking... it's just uneven glue (or epoxy, or whatever it's called in this case).  If you look at edges other than the top, you can see similar unevenness, but it's clear that it is because of the glue.  The left side of the bottom left chip in this zoom is an excellent example.
full member
Activity: 198
Merit: 100
March 11, 2013, 01:17:56 PM
#87
Enigma pointed to strange looking soldering points, but:
- they surely use mostly the edge pins of the chip (because of quick QFN to FCBGA conversion), leaving  most of the middle pins unused;
- Enigma used a photo of a board which was put through the oven without chips, not the one just prepared to place them;
- the photo was blurry and unfocused, so Enigma's conclusions are plain guesswork.
I have a comment for each of your 3 points.

1) This is simply wrong.  When converting from QFN to FCBGA, the upper layer of metal on the silicon is changed to a miniature version of the BGA package.  Proof of this is the photos of the wire bonding test die.  The attachment points are (now) in an array, not along the edge.  Note that the die can have typically more or sometimes less connections than the final BGA package.  The BGA package is simply a very tiny multi-layer PCB that translates the chip balls/bumps to the package ball grid on the bottom.

2) True as far as I can tell.

3) Guesswork?  Maybe.  Maybe not.

I will add that putting vias in the middle of the BGA pads can be problematic.  But I know of assembly houses that can effectively and properly deal with this.  Another option is to get the blank boards with filled vias.  (Not something that the PCBs in the photos have.)  We recently had to do this on a project I'm working on.
full member
Activity: 198
Merit: 100
March 11, 2013, 12:58:53 PM
#86
What, they didn't apply the glue that holds the metal caps in place evenly?
 Huh

In these FCBGA packages there are no metal caps.  The shiny square you see is the back of the actual silicon chip itself.  Since these are quickly assembled prototypes, I would not weigh any possible defects in the underfill too heavily. 

Yes it is true that poor underfill will cause long term reliability problems in the production parts.  What you see photos of here are not the production parts - just test units from the first production run.  In other words, I'm guessing these are likely units they made while they were refining the underfill process.
hero member
Activity: 952
Merit: 1009
March 11, 2013, 12:45:43 PM
#85
It's apparently a rush job on the underfill. If it looks like that on the edges I don't even want to know how many voids will be underneath those things.

Of course according to Josh those are JPG artifacts, nothing to worry about, everything's fine in Butterfly Land.

If only he knew how JPG artifacts look like.

(Hint: Nothing like this. I can tell by the pixels and having seen quite some artifacts in my time)

I'm joking of course, though not about the underfill and Josh's limited understanding of image compression.
hero member
Activity: 840
Merit: 1000
March 11, 2013, 12:33:24 PM
#84
Good god



What, they didn't apply the glue that holds the metal caps in place evenly?
 Huh
legendary
Activity: 1988
Merit: 1012
Beyond Imagination
legendary
Activity: 966
Merit: 1000
March 10, 2013, 09:58:22 PM
#82
Guys, relax.
There won't be much thermal cycling as a typical miner will be on 100% of the time.
Unlike a typical PC which is turned on once a day and turned off once a day.

It won't take much either.  Just the normal day to night swings will do it.  I have seen 100s of thousands of underfilled chips over 10 process generations, many with underfill defects, and none of them looked as bad as these.

The black blotch shown on greyhawk's zoom is a scrap part.  That is underfill, it will prevent proper cooling and is impossible to sand off without cracking the brittle silicon.


Even a few seconds of downtime will cause a huge thermal swing in such a chip.  Imagine a pool server that's overloaded, or a flaky internnet connection.

Here are some temperature graphs from a couple of my GPU miners.  The first one has a better internet connection than the second.



legendary
Activity: 1512
Merit: 1000
March 10, 2013, 09:51:54 PM
#81
After all he is a specialist payed with 1000$/day to spot this kind of problems.

I can't comment on the validity of his statements, but ~1000/day isn't unheard of.
legendary
Activity: 1400
Merit: 1000
I owe my soul to the Bitcoin code...
March 10, 2013, 09:31:34 PM
#80
Yes, because that completely invalidates the garbage underfill job, and the chipped dies that Greyhawk pointed out.

I do not think the dies are chipped, it looks more like the underfill is incomplete to the edge in places.
hero member
Activity: 756
Merit: 501
March 10, 2013, 07:01:42 PM
#79

I recognized it as a nano-sprinkler straight away. Genius!
Sprinkler you say? Good, ´cos Entropy got me worried for a second. After all he is a specialist payed with 1000$/day to spot this kind of problems.

Yes, because that completely invalidates the garbage underfill job, and the chipped dies that Greyhawk pointed out.

Keep dreaming my friend.
hero member
Activity: 700
Merit: 500
March 10, 2013, 06:46:34 PM
#78

I recognized it as a nano-sprinkler straight away. Genius!
Sprinkler you say? Good, ´cos Entropy got me worried for a second. After all he is a specialist payed with 1000$/day to spot this kind of problems.
hero member
Activity: 756
Merit: 501
March 10, 2013, 06:44:01 PM
#77
Are you guys sure this black spec is on the chip itself? Looks to me like something on the ceiling reflected on the chip....



Good eye.  I think you might be right.
RHA
sr. member
Activity: 392
Merit: 250
March 10, 2013, 06:40:19 PM
#76
Are you guys sure this black spec is on the chip itself? Looks to me like something on the ceiling reflected on the chip....
I'd thought the same, so I wrote "if made of". I think Entropy is strongly biased against BFL. His warnings would be good if someone could correct something because of them. Else, it's spreading of FUD.

We have to wait and see. All pre-ordering was a kind of betting and the result is still not certain.
legendary
Activity: 1918
Merit: 1570
Bitcoin: An Idea Worth Spending
March 10, 2013, 06:32:47 PM
#75
Are you guys sure this black spec is on the chip itself? Looks to me like something on the ceiling reflected on the chip....


That was my reasoning which is why I did not arrow it.

I recognized it as a nano-sprinkler straight away. Genius!
hero member
Activity: 952
Merit: 1009
March 10, 2013, 06:25:55 PM
#74
Are you guys sure this black spec is on the chip itself? Looks to me like something on the ceiling reflected on the chip....


That was my reasoning which is why I did not arrow it.
sr. member
Activity: 406
Merit: 250
March 10, 2013, 06:22:30 PM
#73
Are you guys sure this black spec is on the chip itself? Looks to me like something on the ceiling reflected on the chip....



Maybe it's an overhead fire sprinkler ?  Those look like ceiling panels and the spinkler is in the center of the panel.  Next to the overhead lightning panel.

hero member
Activity: 700
Merit: 500
March 10, 2013, 06:06:41 PM
#72
Are you guys sure this black spec is on the chip itself? Looks to me like something on the ceiling reflected on the chip....

RHA
sr. member
Activity: 392
Merit: 250
March 10, 2013, 05:38:43 PM
#71
It won't take much either.  Just the normal day to night swings will do it.  I have seen 100s of thousands of underfilled chips over 10 process generations, many with underfill defects, and none of them looked as bad as these.
The black blotch shown on greyhawk's zoom is a scrap part.  That is underfill, it will prevent proper cooling and is impossible to sand off without cracking the brittle silicon.
Entropy, take it easy. This black blotch, if made of underfill, will prevent ideal cooling. When using with thermal paste or pads, the cooling will be proper enough.
I can't say nothing about the voids, you are the professional, but the day-night temperature changes should be compensated by variable speed of the fan, keeping the board temperature quite stable.

Enigma pointed to strange looking soldering points, but:
- they surely use mostly the edge pins of the chip (because of quick QFN to FCBGA conversion), leaving  most of the middle pins unused;
- Enigma used a photo of a board which was put through the oven without chips, not the one just prepared to place them;
- the photo was blurry and unfocused, so Enigma's conclusions are plain guesswork.
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