Marcus: The die size will be...very large.
That sounds like trouble waiting to happen.
I agree. This plus the lack of chip testing before mounting to the boards are the two things that concern me the most. Here's why: yield. There are two primary sources of yield loss (bad chips).
1) Process problems. Ex: Too much etching of metal (opens), not enough etching of metal (shorts), and similar issues with other layers (transistors and layer interconnects). These are usually noticed and/or fixed by the fab because they add test structures in between the chips in the scribe lanes and/or in unused areas of the chips. During each step of the wafer production, they test these test structures to make sure that that particular step was done right. If done wrong, the wafers are scrapped or sometimes the error can be corrected. However, there can be a uniformity issue where the die on one part of the wafer are good, while all the die in another area are bad.
2) Random defects - figuratively (sometimes literally) "specks of dust" on the wafers. Think of these this way. Imagine putting a piece of graph paper on the wall (representing the wafer and the small squares are the individual die) and throwing darts at it randomly. Lets say you throw 50 darts and the hole left by each dart represents a random defect. If the graph paper has small squares (1000 per sheet of paper), then you have 50 bad die, 950 good die for 95% yield of good die. Now imagine the squares (die) are 10x bigger so there are only 100 die per wafer. Now 50 defects gives 50 bad die and 50 good ones for 50% yield. Thus, larger die size impacts yield negatively. Realize the numbers here were chosen for simplicity but the effect is VERY real.
Small die --> high yields --> no chip testing --> probably good.
Large die --> low yields --> no chip testing --> not a good idea in my opinion.
ORSoC is relying on the concept of using a large number of cores per chip and turning off the bad ones. The idea is that you can turn a bad die back into a good one. This is generally an acceptable strategy and one that BFL is successfully using. Depending on ORSoc's actual die size, the process yields, and the specific method of disabling cores, they might pull it off. However as someone else mentioned in this thread, there are sometimes chips that are COMPLETELY dead - just a shorted blob of metal and completely worthless unless you want something to blow up power supplies.
Those really should be screened out at a minimum. And if you're doing that, you might as well do a full chip test with binning.
Note: I'm not condemning the strategy that ORSoc is using. It might work. I would be a whole lot more comfortable if they were doing chip testing.
Disclaimer: I am a BFL customer. I have not ordered any KnC product yet but I am seriously considering it. If I had the cash on hand I might have already ordered. Perhaps BTC I mine with my BFL hardware will go to KnC.