Topic: BTCMiner - Open Source Bitcoin Miner for ZTEX FPGA Boards, 215 MH/s on LX150 (Read 161727 times)

Hey, what about http://www.blakecoin.org/, has anyone tried it with their zTex? I only have 1.15x, does the bitstream work on those?

You may not believe it, but there is hardware which is not only developed for BTC mining. Screw drivers, for example.

Estimated hash rate of these FPGA's is indeed 350 to 400 MH/s

ZTEX not gonna adapt BTCMiner to use with your new board Artix7?

Hehe, zTex strikes back!? What would these deliver 400MH/s?

I don't get this, 3 months since bitfury released the source for their 300MH bitstream, how come ztex don't release it?!

https://github.com/Taugeran/Bitfury

Dear FPGA miners,

I am trying to build the "open source" ZTEX project ZtexBTCMiner-120703

http://www.ztex.de/btcminer/ZtexBTCMiner-120703.tar.bz2

under ISE 14.1 and I am having difficulty making the LX150 Bitfile for the 4 FPGA version of ztex_ufm1_15y1.  I am using ISE Project Navigator 14.1 configured as follows:
 
SET AS TOP MODULE:                                   ztex_ufm1_15y1 (ztex_ufm1_15y1.v)
INCLUDED UCF FILE:                                     ztex_ufm1_15y1.ucf
TARGET DEVICE:                                          xc6slx150-3csg484

The problems are:

(1) I would like to get some recommended part numbers for low profile heatsinks, I notice that Digi-key does not carry Radian.    
(2) Route:441 - The router has detected a very high timing score (7681590) for this design. It is extremely unlikely the router will be able to meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the implementation or synthesis of logic in the critical timing path. If you would prefer the router continue trying to meet timing and you are willing to accept a long run time set the option "-xe c" to override the present behavior.

(Router eventually gives up)

There is no ISE project file in the source tree, and Dr. Z has given his assurance that the .ucf file is complete.

Can anyone please give me some direction on how to build this bitfile correctly, apart from what I am doing as described above?  I have searched these forums and come up with nada. 6500 subproject on GitHub builds just fine, using the same setup.

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/X6000_ztex_comm4

The reason I want to build my own bitfile should be obvious to the thirsty...and fellow abductees.  Damn probes. Just wait until we get one of them onto a steel table.

I wanted to build the source using ISE - it's bombing out due to the defines in sha256_pipes2.v.  Has anyone else run in to this problem?

For example,
data15_p1 <= `S1( S[i-1].data[`IDX(15)] );                                 // 3

Pukes with
ERROR:HDLCompiler:806 - "C:/bitminer-src/fpga/sha256_pipes2.v" Line 89: Syntax error near "[".

As well as several others.  From what I can tell, XST is quite happy with this syntax just a few lines prior.

In the end, the problem was with the power supplies... both little cheap wall warts. After switching to a 12V 5A regulated power supply, no problems. Maybe not as efficient in term of power, but the boards have mined reliably for days without having to restart anything.