BTCMiner - Open Source Bitcoin Miner for ZTEX FPGA Boards, 215 MH/s on LX150 - page 13.

antirack

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Quote from: gr0bi42 on June 10, 2012, 03:01:15 AM

Anyone interested in this?

Code:

001-1: ztex_ufm1_15y1-04A346BE51-2: Change frequency from 208.00MHz to 212.00MHz
001-1: ztex_ufm1_15y1-04A346BE51-2: Change frequency from 212.00MHz to 216.00MHz
001-1: ztex_ufm1_15y1-04A346BE51-2: Change frequency from 216.00MHz to 208.00MHz

Good job gr0bi42! Are you using Ubuntu and what JDK are you using?

gr0bi42

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Anyone interested in this?

Code:

001-1: ztex_ufm1_15y1-04A346BE51-2: Change frequency from 208.00MHz to 212.00MHz
001-1: ztex_ufm1_15y1-04A346BE51-2: Change frequency from 212.00MHz to 216.00MHz
001-1: ztex_ufm1_15y1-04A346BE51-2: Change frequency from 216.00MHz to 208.00MHz

Here is the patch agains BTCMiner.java (+ 2 removed warnings due to garbage a character in the comment):

Code:

--- bitminer-src/BTCMiner.java	2012-04-17 22:55:56.000000000 +0200
+++ bitminer-new/BTCMiner.java	2012-06-10 09:08:51.429426206 +0200
@@ -126,7 +126,7 @@
 	start();
     }
 
-// ******* checkNew ***********************************************************
+// ******* checkNew ************************************************************
     synchronized public boolean checkNew ( byte[] data ) throws NumberFormatException {
 	if ( data.length < 36 )
 	    throw new NumberFormatException("Invalid length of data");
@@ -1510,10 +1510,13 @@
 		bestR = r;
 	    }
 	}
-	
 	if ( bestM != freqM ) {
+	    if ( freqM > 0 ) {
+		msg ( "Change frequency from " + String.format("%.2f",(freqM+1)*(freqM1)) + "MHz to " + String.format("%.2f",(bestM+1)*(freqM1)) + "MHz" );
+	    } else {
+		msg ( "Set frequency to " + String.format("%.2f",(bestM+1)*(freqM1)) + "MHz" );
+	    }
 	    freqM = bestM;
-	    msg ( "Set frequency to " + String.format("%.2f",(freqM+1)*(freqM1)) +"MHz" );
 	    setFreq( freqM );
 	}
 
@@ -1725,7 +1728,7 @@
 	return "bitfile=" + bitFileName + "   f_default=" + String.format("%.2f",freqM1 * (freqMDefault+1)) + "MHz  f_max=" + String.format("%.2f",freqM1 * (freqMaxM+1))+ "MHz  HpC="+hashesPerClock+"H";
     }
 
-// ******* resetCounters ******************************************************
+// ******* resetCounters *******************************************************
     public void resetCounters () {
 	while ( freqMDefault100 )
 	    freqMDefault++;

Compile it by yourself or feel free to trust me and just download it from: http://www.file-upload.net/download-4432190/ZtexBTCMiner.jar.html

antirack

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Thanks a lot gr0bi42, that's very helpful. I can give it a try tomorrow morning on my Ubuntu box. I can then still give it a try on my Windows PC to see how make etc works there. I'll let you know how it goes.

gr0bi42

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Quote from: antirack on June 09, 2012, 12:59:40 AM

(I'd like to do this on my Windows box for now)

Oh, sorry. No idea how it works on Windows. Maybe you can run a Linux with VirtualBox. The resulting jar-file of course will run on Windows.

gr0bi42

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Quote from: antirack on June 09, 2012, 12:59:40 AM

Is Ztex the only one developing the Java BTCMiner?

Could it be run from source code or does one need to package it into the .jar file?

Is there anyone here who could give me a quick rundown what's required to get this to work after I made some changes to the source code (mostly to the logging functions for now)? I can donate some BTC in return! (I'd like to do this on my Windows box for now)

Thanks!

Ok, a quick'n'dirty howto...

Download(1): http://www.ztex.de/btcminer/ZtexBTCMiner-120417.tar.bz2 (BTCMiner Source)
Download(2): http://www.ztex.de/downloads/ztex-120412.tar.bz2 (EZ USB SDK)
Download(3): http://www.ztex.de/btcminer/ZtexBTCMiner-120417.jar (needed to extract bit-files)

Code:

> mkdir btcminer
> tar xfj ~/Downloads/ZtexBTCMiner-120417.tar.bz2
> tar xfj ~/Downloads/ztex-120412.tar.bz2
> mkdir tmp
> cd tmp
> jar xf ~/Downloads/ZtexBTCMiner-120417.jar
> cd ../bitminer-src

Now edit the Makefile and adjust ZTEXPREFIX to:

Code:

>vi Makefile
ZTEXPREFIX=../ztex

Copy the bit-files:

Code:

> cp ../tmp/fpga/*.bit fpga/

And finally:

Code:

> make
> java -cp ZtexBTCMiner.jar BTCMiner -host http://: -u  -p  -m c

If you change something just do another make.

antirack

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Is Ztex the only one developing the Java BTCMiner?

Could it be run from source code or does one need to package it into the .jar file?

Is there anyone here who could give me a quick rundown what's required to get this to work after I made some changes to the source code (mostly to the logging functions for now)? I can donate some BTC in return! (I'd like to do this on my Windows box for now)

Thanks!

BR0KK

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i have no clue

Maybe catfish can help me out

€: Saw the great work from eldertyrell today. Will there be a tricone bitstream for Ztex boards?

ztex

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Quote from: BR0KK on May 15, 2012, 03:59:02 PM

Thank u ill try it

€: with my small knowledge of OSX (and linux) i can't get it to mine with osx.... Ill try it again but it would be nice if you could add OSX support some day in the future.

€1:
It kinda runs now. I copied the file to /library/Java/Extensions

in Terminal i can start BTCMiner now,. but it won't recognize any of my boards ....

if i run it with -i it displays "no devices found"

€2:
i installed libusb but can not talk my devices to mine with btcminer natively. Still no devices found.

Looks like USB problems. I'm not familiar with Mac, but a wrong / non-existent libusb should be reported. Are there maybe permission constraints?

BR0KK

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Thank u ill try it

€: with my small knowledge of OSX (and linux) i can't get it to mine with osx.... Ill try it again but it would be nice if you could add OSX support some day in the future.

€1:
It kinda runs now. I copied the file to /library/Java/Extensions

in Terminal i can start BTCMiner now,. but it won't recognize any of my boards ....

if i run it with -i it displays "no devices found"

€2:
i installed libusb but can not talk my devices to mine with btcminer natively. Still no devices found.

ztex

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Quote from: BR0KK on May 14, 2012, 10:33:55 AM

Nice to know but where exactly am i supposed to copy that file to? Working directory <--Where do i find that?

A complete link to a folder would be nice

The working directory is the directory from where you start an application. It can be any directory.

BR0KK

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Nice to know but where exactly am i supposed to copy that file to? Working directory <--Where do i find that?

A complete link to a folder would be nice

ztex

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Quote from: CA Coins on May 13, 2012, 08:05:27 PM

Hey Catfish, agree on the build quality of these boards. Would also love to get binaries for running them on OS X. Thanks.

See http://wiki.ztex.de/doku.php?id=en:software:porting&#macos_port

CA Coins

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Hey Catfish, agree on the build quality of these boards. Would also love to get binaries for running them on OS X. Thanks.

catfish

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Quote from: ztex on May 11, 2012, 01:33:34 AM

Quote from: catfish on May 09, 2012, 04:46:07 PM

My theory is that these are poor quality USB hubs, and coupled with the 1-into-5 barrel plug splitter I use (its cable gets stupidly hot, so I am going to have to buy individual barrel plugs and wire them up myself to PCIe power adapters using your recommendation), I may be overloading the USB bus ground.

Is this likely? Or would overloading the USB ground simply 'let the smoke out of the wires'? Whilst my second test pentagon (I'm building my FPGA arrays in sets of five, in order to use 60W ATX power cables per set) has stupidly hot daisy-chain power cables, it hasn't failed yet.... though I'll be re-building it tomorrow. Incidentally, the 2.1/5.5 barrel splitter that gets really hot is a local Maplin part, not your Ztex part, which seems to stay cool. Must be better quality cable.

The power cables must not get warm or even hot.

For powering your amount of boards I recommend this method: http://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:cluster_power_supplies#usb-fpga_module_115x_and_115dlarge_clusters .

Most critical are the GND lines. As higher their resistance as more current flows through the USB shielding. Therefore I do not recommend daisy-chaining the power cables for larger amounts of boards.

Excellent, thanks Stefan.

Though I must comment that your boards are *VERY* resilient - I've not been very well and haven't actually got any of the jobs done, yet 10 of the 1.15x boards, running with cheap USB hubs, hot-to-touch daisy-chain power cables (I cut one open to check the wire gauge... it's like ethernet cable), in my cellar office with ambient temperature of 38˚C (not a typo, that's 38˚C ) - all 10 have been working perfectly and the slowest board of the lot still manages 200 MHz and megahash/sec.

Absolutely blinding quality. Once I can acquire enough 2.1/5.5 barrel plugs and solder them up to 18AWG wires, I've got a spare 850W ATX PSU which should be able to power them all.

Oh yeah - and all 10 of my currently-running Ztex FPGAs (I have 25 to build) - are being controlled on Mac OS X Snow Leopard. So any potential Ztex buyers who run Apple Macs.... give me a shout and I'll send you 32-bit or 64-bit libraries for the libusb. Java works OK with the Apple runtime. I had to hack Stefan's makefiles but... needs must. Can't be arsed with building another Linux box, and I won't have Windows on my network.

Seriously - for everyone else here - my setup is pretty much the worst stress-test that Stefan's boards could possibly have. Ambient temp is above working temp, 5 of the boards use passive heatsinks with limited airflow, and the other has out-of-spec resistance on the power lines. If Stefan's kit was duff quality then I'd have broken 10 boards by now, but I've had them running for a week without ANY problems. Each 5-board cluster gives over 1 gigahash/sec. Even at these temperatures.

Nice one. Impressed.

BR0KK

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Im a mac user too and would love to get them running by default under mac ... Then i can get rid of my paralells VM

nelisky

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Quote from: catfish on May 11, 2012, 02:56:42 PM

Oh yeah - and all 10 of my currently-running Ztex FPGAs (I have 25 to build) - are being controlled on Mac OS X Snow Leopard. So any potential Ztex buyers who run Apple Macs.... give me a shout and I'll send you 32-bit or 64-bit libraries for the libusb. Java works OK with the Apple runtime. I had to hack Stefan's makefiles but... needs must. Can't be arsed with building another Linux box, and I won't have Windows on my network.

I would be very interested in both the libraries and the recipe to build them myself. Given my ztex boards are running off a tp-link router, I would really like to avoid spinning out my windows or linux VM to update firmwares, and getting java in said router is not something I'm looking forward to do.

ztex

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Quote from: catfish on May 09, 2012, 04:46:07 PM

My theory is that these are poor quality USB hubs, and coupled with the 1-into-5 barrel plug splitter I use (its cable gets stupidly hot, so I am going to have to buy individual barrel plugs and wire them up myself to PCIe power adapters using your recommendation), I may be overloading the USB bus ground.

Is this likely? Or would overloading the USB ground simply 'let the smoke out of the wires'? Whilst my second test pentagon (I'm building my FPGA arrays in sets of five, in order to use 60W ATX power cables per set) has stupidly hot daisy-chain power cables, it hasn't failed yet.... though I'll be re-building it tomorrow. Incidentally, the 2.1/5.5 barrel splitter that gets really hot is a local Maplin part, not your Ztex part, which seems to stay cool. Must be better quality cable.

The power cables must not get warm or even hot.

For powering your amount of boards I recommend this method: http://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:cluster_power_supplies#usb-fpga_module_115x_and_115dlarge_clusters .

Most critical are the GND lines. As higher their resistance as more current flows through the USB shielding. Therefore I do not recommend daisy-chaining the power cables for larger amounts of boards.

catfish

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Hey Stefan

Firstly, many thanks for the swift delivery of the boards, and the excellent packaging. Everything works as expected.

Whilst I've got 10 of the boards running now (5 with Zalman passive heatsinks, 5 with supplied Xilence HSF combos, and I admit I may have used the 'wrong' thermal compound, but they run cooooool), I'm finding that my cheap-and-cheerful 4-port USB2 hubs (bought in bulk, since I knew I'd be needing 10 of them) are unpredictable as hell.

Connect 4 boards to one hub, and the other (plus the hub) to another, and only 3 or 4 (seemingly randomly selected) boards will be visible in scan (-i) mode. Connecting two boards to each 4-port hub, each 4-port hub plugged into the computer, and the 5th board directly connected to the computer, sometimes works.

My theory is that these are poor quality USB hubs, and coupled with the 1-into-5 barrel plug splitter I use (its cable gets stupidly hot, so I am going to have to buy individual barrel plugs and wire them up myself to PCIe power adapters using your recommendation), I may be overloading the USB bus ground.

Is this likely? Or would overloading the USB ground simply 'let the smoke out of the wires'? Whilst my second test pentagon (I'm building my FPGA arrays in sets of five, in order to use 60W ATX power cables per set) has stupidly hot daisy-chain power cables, it hasn't failed yet.... though I'll be re-building it tomorrow. Incidentally, the 2.1/5.5 barrel splitter that gets really hot is a local Maplin part, not your Ztex part, which seems to stay cool. Must be better quality cable.

Once I've done a proper job on powering the boards - using individual barrel plugs fed from PCIe power cables - do you think the USB unreliability will go away?

If not, can you recommend a Ztex-approved USB hub that can be daisy-chained out to the claimed scalability (127 devices on the bus)? Currently, I need a separate computer for every 5 Ztex boards - not due to power supply issues (though power splitting may be the cause), but because simply chaining multiple hubs together to give lots of cascading USB ports doesn't always work.

I expect that this is due to the cheap rubbish I bought from Amazon, but it'd be good to know that this is the case. To connect 25 of your FPGAs to one host computer, do all the USB hubs need to have separate power supplies? If not, can you recommend a suitable known-good USB hub model? I've spent too much on FPGAs to lose it all - especially if due to a £1.50 USB hub with soldering done by a Chinese bloke at the end of a 16 hour shift, shorting out inside the USB hub.

Equally, if using over 3 chained USB hubs requires each hub to be powered, then further expansion will require loads of power sockets just for the USB hub PSUs. Surely in this case, one may as well go without powered hubs and use individual 60W switching-mode PSUs... if one has to have loads of power sockets available anyway? With the whole benefit of using ATX PSUs being clean, protected 12V DC at plenty of current for Ztex FPGA boards, it'd make no sense to require tens of individual PSUs for the necessary USB hubs (which are either 4-port or 7-port according the the USB2 spec, IIRC).

Right now, my systems are hashing away like crazy, but are definitely not as happy as they could be. The power daisy-chain cable is FAR too hot for my comfort, and the USB cables are also hotter than I'd expect.

This is almost certainly due to my cheap initial build - can you recommend a USB hub (preferably one with lots of ports) that you *know* works well with your boards, if powered by ATX PSUs?

all the best
catfish

Turbor

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Ask him about the USB hubs ! Grin

https://bitcointalksearch.org/topic/m.891599

gr0bi42

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Quote from: CA Coins on May 07, 2012, 05:30:46 AM

Quote from: ztex on May 07, 2012, 05:20:41 AM

Quote from: CA Coins on May 07, 2012, 04:49:07 AM

Quote

The effect can be reduced by reducing the number of devices per thread (parameter -n). But the only way to solv this is to choose a faster pool server.

Does reducing the number of devices also help if you're seeing overflows?

Usually yes. This depends on the amount of CPU cores, the size of the cluster and the OS. It's probably not wise to run 200 threads on a single core Atom.

Thanks, I will give it a try. Also, not sure if anybody has already mentioned, the block log option is listed as -lb on the help instead of -bl

EDIT: Just terminated the process remotely with control-c. When trying to restart, got:

Code:

ztex_ufm1_15y1-2012-L5-A1: New device: bitfile=ztex_ufm1_15y1   f_default=200.00MHz  f_max=240.00MHz  HpC=1.0H
Warning: Error uploading bitstream: FPGA configuration failed: DONE pin does not go high, possible USB transfer errors (INIT_B_HIST=222): Retrying it ...
Warning: Error uploading bitstream: FPGA configuration failed: DONE pin does not go high, possible USB transfer errors (INIT_B_HIST=222): Retrying it ...
Warning: High speed FPGA configuration failed, trying low speed mode:Error uploading bitstream: FPGA configuration failed: DONE pin does not go high, possible USB transfer errors (INIT_B_HIST=222): Trying low speed mode
Warning: Error uploading bitstream: FPGA configuration failed: DONE pin does not go high (size=4220313 ,  0 bytes got lost;  checksum=3 , should be 3;  INIT_B_HIST=222): Retrying it ...
Warning: Error uploading bitstream: FPGA configuration failed: DONE pin does not go high (size=4220313 ,  0 bytes got lost;  checksum=3 , should be 3;  INIT_B_HIST=222): Retrying it ...

I have noticed this before with the quads that went away with a power-cycle. any thoughts?

+1. Got the same problem several times. Boards are mining without problems. After stop of BTCMiner or reboot sometimes I got this "FPGA configuration failed" errors. Last time yesterday. I disconnected the boards from power for about 3 secs (power off, wait until fan stops, power on). Same error again. Once again power off, waiting around 30 secs, power on => success. Boards are mining fine since then.

Topic: BTCMiner - Open Source Bitcoin Miner for ZTEX FPGA Boards, 215 MH/s on LX150 - page 13. (Read 161727 times)