Topic: BTCMiner - Open Source Bitcoin Miner for ZTEX FPGA Boards, 215 MH/s on LX150 - page 32. (Read 161727 times)
August 29, 2011, 09:54:55 PM
August 29, 2011, 08:21:03 PM
quotation already asked, pls check the info ztex mailbox.
August 29, 2011, 08:20:46 PM
Hi,
It was not me. I published my code on Friday at http://www.ztex.de/btcminer/. Maybe someone read it and posted it on IRC.
BTCMiner supports dynamic overclocking based on error measurement, i.e. the software scales the frequency such that a maximum rate of valid hashes is generated.
Aha - I remember you mentioning this on IRC. Cunning! Didn't realise that you were the person behind the ZTEX FPGA boards though...It was not me. I published my code on Friday at http://www.ztex.de/btcminer/. Maybe someone read it and posted it on IRC.
August 29, 2011, 08:17:56 PM
Things are getting interesting for FPGA mining.
Are you open to sell me a couple of boards with a nice discount, and get a deep review on it ?
I'm a 25 ghps experienced miner.
Development of FPGA boards (and selling them) is my business. Are you open to sell me a couple of boards with a nice discount, and get a deep review on it ?
I'm a 25 ghps experienced miner.
There are no restrictions (pre-orders, reservations). If the boards are on stock (http://shop.ztex.de) you can purchase them.
1.15d boards are an stock. The cost optimized version (1.15x) is scheduled for later half of September.
The single unit and 25 unit prices are stated in the intro. For other amounts ask for a quotation: http://shop.ztex.dehttp://shop.ztex.de/contact_us.php.
August 29, 2011, 08:16:47 PM
As I wrote you in my PM, I started with some C code. I computed using a constant input value (no counter) and verified the result with the result from the C code. After I got my first correct results I read about your project.
I implemented the counting stuff at a late state, after I read your code and code from other (non-FPGA) projects. If you say, you are the only one who uses this term, this name has been stolen from you.
You searched for similarities. The only non-trivail one you found is the term "golden_nonce". Did you also search for trivial differences i.e. differences that would not occur is my code is derived from yours?
You want me to add a reference to your project into my Copyright note. This requires that at least major parts of my code are derived from your project. This is not the case. You also agreed to this in your PM:
If I would add such a reference, I would have to start with the C Code I mentioned. And I'm sure, you would have to do the same, because this algorithm is not yours and you also copied parts of your implementation from other sources (namely the k array).
-----BEGIN PGP SIGNED MESSAGE-----
1) The use of the term golden_nonce is unique to me, and has not to my knowledge, nor the knowledge of Google, ever been used by anyone else. It appears several times in your code.
1) The use of the term golden_nonce is unique to me, and has not to my knowledge, nor the knowledge of Google, ever been used by anyone else. It appears several times in your code.
I implemented the counting stuff at a late state, after I read your code and code from other (non-FPGA) projects. If you say, you are the only one who uses this term, this name has been stolen from you.
Quote
2) Your use of an appended _w is unique to my Verilog coding style.
It is common to distunguish between wires and registers by prefixes or suffixes "w" and "r". Are there other similarities between the register / signal names. If not, do you think I have renamed your registers bur just forgot the prefixes or suffixes?Quote
3) Your use of a monolithic localparam named Ks in sha256_pipes.v, with the constants occurring in reverse order using the concat operator is unique to my project.
The k array is copied from C source code. I can give you several examples where this array occurs in exactly the same order. This array is definitely not your invention.Quote
4) The use of a define named IDX is an exact duplicate of my usage, again unique to my coding style.
There is only this one way to implement the INDEX macro.You searched for similarities. The only non-trivail one you found is the term "golden_nonce". Did you also search for trivial differences i.e. differences that would not occur is my code is derived from yours?
You want me to add a reference to your project into my Copyright note. This requires that at least major parts of my code are derived from your project. This is not the case. You also agreed to this in your PM:
Quote
Obviously the pieces of the code you have written belong to yourself
If I would add such a reference, I would have to start with the C Code I mentioned. And I'm sure, you would have to do the same, because this algorithm is not yours and you also copied parts of your implementation from other sources (namely the k array).
August 29, 2011, 06:54:35 PM
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hello ztex,
I felt it best to bring this to the public forum.
August 29th, 2011
In your reply PM to me, you stated that none of your Verilog code is a derivative of my work. However, I am very concerned by many similarities between your newly released Verilog code, and my GPL3 code which has been around since May 20th, 2011. I hope these are just coincidences, but to express my concerns I have listed details below.
1) The use of the term golden_nonce is unique to me, and has not to my knowledge, nor the knowledge of Google, ever been used by anyone else. It appears several times in your code.
2) Your use of an appended _w is unique to my Verilog coding style.
3) Your use of a monolithic localparam named Ks in sha256_pipes.v, with the constants occurring in reverse order using the concat operator is unique to my project.
4) The use of a define named IDX is an exact duplicate of my usage, again unique to my coding style.
I am listing an exact copy of your code below, as of this date, and links to code belonging to my github repo. Please note that there are many variations of the code available on my repo, and also note that much of the code on my repo is contributed by myself, and various other wonderful developers.
miner128.v
sha256_pipes.v
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: hash pipelines
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x}[1:0],{x}[31:2]} ^ {{x}[12:0],{x}[31:13]} ^ {{x}[21:0],{x}[31:22]} )
`define E1(x) ( {{x}[5:0],{x}[31:6]} ^ {{x}[10:0],{x}[31:11]} ^ {{x}[24:0],{x}[31:25]} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x}[6:4] ^ {x}[17:15], {{x}[3:0], {x}[31:7]} ^ {{x}[14:0],{x}[31:18]} ^ {x}[31:3] } )
`define S1(x) ( { {x}[16:7] ^ {x}[18:9], {{x}[6:0], {x}[31:17]} ^ {{x}[8:0],{x}[31:19]} ^ {x}[31:10] } )
module sha256_pipe_base ( clk, state, data, out );
parameter STAGES = 64;
input clk;
input [255:0] state;
input [511:0] data;
output [255:0] out;
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
genvar i;
generate
for (i = 0; i <= STAGES; i = i + 1) begin : S
wire [479:0] w_data;
wire [223:0] w_state;
wire [31:0] w_t1, w_data14;
if(i == 0)
sha256_stage0 #(
.K_NEXT(Ks[`IDX(63)]),
.STAGES(STAGES)
) I (
.clk(clk),
.i_data(data),
.i_state(state),
.o_data(w_data),
.o_state(w_state),
.o_t1(w_t1),
.o_data14(w_data14)
);
else
sha256_stage #(
.K_NEXT(Ks[`IDX((127-i) & 63)]),
.STAGES(STAGES)
) I (
.clk(clk),
.i_data(S[i-1].w_data),
.i_state(S[i-1].w_state),
.i_t1(S[i-1].w_t1),
.i_data14(S[i-1].w_data14),
.o_data(w_data),
.o_state(w_state),
.o_t1(w_t1),
.o_data14(w_data14)
);
end
endgenerate
reg [31:0] state7;
always @ (posedge clk)
begin
state7 <= S[STAGES-1].w_state[`IDX(6)];
end
assign out[255:224] = state7;
assign out[223:0] = S[STAGES].w_state;
endmodule
module sha256_pipe66 ( clk, state, state2, data, hash );
input clk;
input [255:0] state, state2;
input [511:0] data;
output reg [255:0] hash;
wire [255:0] out;
sha256_pipe_base #( .STAGES(64) ) P (
.clk(clk),
.state(state),
.data(data),
.out(out)
);
always @ (posedge clk)
begin
hash[`IDX(0)] <= state2[`IDX(0)] + out[`IDX(0)];
hash[`IDX(1)] <= state2[`IDX(1)] + out[`IDX(1)];
hash[`IDX(2)] <= state2[`IDX(2)] + out[`IDX(2)];
hash[`IDX(3)] <= state2[`IDX(3)] + out[`IDX(3)];
hash[`IDX(4)] <= state2[`IDX(4)] + out[`IDX(4)];
hash[`IDX(5)] <= state2[`IDX(5)] + out[`IDX(5)];
hash[`IDX(6)] <= state2[`IDX(6)] + out[`IDX(6)];
hash[`IDX(7)] <= state2[`IDX(7)] + out[`IDX(7)];
end
endmodule
module sha256_pipe62 ( clk, data, hash );
parameter state = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
input clk;
input [511:0] data;
output [31:0] hash;
wire [255:0] out;
sha256_pipe_base #( .STAGES(61) ) P (
.clk(clk),
.state(state),
.data(data),
.out(out)
);
assign hash = out[`IDX(4)];
endmodule
module sha256_pipe65 ( clk, state, data, hash );
input clk;
input [255:0] state;
input [511:0] data;
output [255:0] hash;
wire [255:0] out;
sha256_pipe_base #( .STAGES(64) ) P (
.clk(clk),
.state(state),
.data(data),
.out(out)
);
assign hash = out;
endmodule
module sha256_stage0 ( clk, i_data, i_state, o_data, o_state, o_t1, o_data14 );
parameter K_NEXT = 32'd0;
parameter STAGES = 64;
input clk;
input [511:0] i_data;
input [255:0] i_state;
output reg [479:0] o_data;
output reg [223:0] o_state;
output reg [31:0] o_t1, o_data14;
wire [31:0] s0;
always @ (posedge clk)
begin
o_data <= i_data[511:32];
o_state <= i_state[223:0];
o_t1 <= i_state[`IDX(7)] + i_data[`IDX(0)] + K_NEXT;
o_data14 <= `S0( i_data[`IDX(1)] ) + i_data[`IDX(0)];
end
endmodule
module sha256_stage ( clk, i_data, i_state, i_t1, i_data14, o_data, o_state, o_t1, o_data14 );
parameter K_NEXT = 32'd0;
parameter STAGES = 64;
input clk;
input [31:0] i_t1, i_data14;
input [479:0] i_data;
input [223:0] i_state;
output reg [479:0] o_data;
output reg [223:0] o_state;
output reg [31:0] o_t1, o_data14;
wire [31:0] t1 = `E1( i_state[`IDX(4)] ) + `CH( i_state[`IDX(4)], i_state[`IDX(5)], i_state[`IDX(6)] ) + i_t1;
wire [31:0] t2 = `E0( i_state[`IDX(0)] ) + `MAJ( i_state[`IDX(0)], i_state[`IDX(1)], i_state[`IDX(2)] );
wire [31:0] data14 = `S1( i_data[`IDX(13)] ) + i_data[`IDX(8)] + i_data14;
always @ (posedge clk)
begin
o_data[447:0] <= i_data[479:32];
o_data[`IDX(14)] <= data14;
o_state[`IDX(0)] <= t1 + t2;
o_state[`IDX(1)] <= i_state[`IDX(0)];
o_state[`IDX(2)] <= i_state[`IDX(1)];
o_state[`IDX(3)] <= i_state[`IDX(2)];
o_state[`IDX(4)] <= i_state[`IDX(3)] + t1;
o_state[`IDX(5)] <= i_state[`IDX(4)];
o_state[`IDX(6)] <= i_state[`IDX(5)];
o_t1 <= i_state[`IDX(6)] + i_data[`IDX(0)] + K_NEXT;
o_data14 <= `S0( i_data[`IDX(1)] ) + i_data[`IDX(0)];
end
endmodule
Similar to: https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/blob/master/src/sha256_transform.v
Please do not interpret this as me calling you a liar. You have obviously put a lot of work into your code and made numerous enhancements. I honestly wish you the best success with it. These numerous similarities just set off a lot of alarm bells for me and I hope you understand that. Help me to figure out why my coding style has leaked into your code and I will feel a lot better.
Thank you,
~fpgaminer
NOTE: GPG signed based on a plain-text copy of the text above. Just copy-paste the plain-text as it appears on the forum, so that BBCODE formatting is not included, to perform GPG signature verification.
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Hash: SHA1
Hello ztex,
I felt it best to bring this to the public forum.
August 29th, 2011
In your reply PM to me, you stated that none of your Verilog code is a derivative of my work. However, I am very concerned by many similarities between your newly released Verilog code, and my GPL3 code which has been around since May 20th, 2011. I hope these are just coincidences, but to express my concerns I have listed details below.
1) The use of the term golden_nonce is unique to me, and has not to my knowledge, nor the knowledge of Google, ever been used by anyone else. It appears several times in your code.
2) Your use of an appended _w is unique to my Verilog coding style.
3) Your use of a monolithic localparam named Ks in sha256_pipes.v, with the constants occurring in reverse order using the concat operator is unique to my project.
4) The use of a define named IDX is an exact duplicate of my usage, again unique to my coding style.
I am listing an exact copy of your code below, as of this date, and links to code belonging to my github repo. Please note that there are many variations of the code available on my repo, and also note that much of the code on my repo is contributed by myself, and various other wonderful developers.
miner128.v
Code:
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: double hash miner
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module miner128 (clk, reset, midstate, data, golden_nonce, nonce2, hash2);
parameter NONCE_OFFS = 32'd0;
parameter NONCE_INCR = 32'd1;
parameter NONCE2_OFFS = 32'd0;
input clk, reset;
input [255:0] midstate;
input [95:0] data;
output reg [31:0] golden_nonce, hash2, nonce2;
reg [31:0] nonce;
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_pipe66 p1 (
.clk(clk),
.state(midstate),
.state2(midstate),
.data({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash(hash)
);
sha256_pipe62 p2 (
.clk(clk),
.data({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash(hash2_w)
);
always @ (posedge clk)
begin
if ( reset )
begin
nonce <= 32'd129 + NONCE_OFFS;
nonce2 <= NONCE_OFFS + NONCE2_OFFS;
golden_nonce <= 32'd0;
end else begin
nonce <= nonce + NONCE_INCR;
nonce2 <= nonce2 + NONCE_INCR;
if ( hash2 == 32'ha41f32e7 )
begin
golden_nonce <= nonce2;
end
end
hash2 <= hash2_w;
end
endmodule
Similar to: https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/blob/master/src/fpgaminer_top.vbtcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: double hash miner
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module miner128 (clk, reset, midstate, data, golden_nonce, nonce2, hash2);
parameter NONCE_OFFS = 32'd0;
parameter NONCE_INCR = 32'd1;
parameter NONCE2_OFFS = 32'd0;
input clk, reset;
input [255:0] midstate;
input [95:0] data;
output reg [31:0] golden_nonce, hash2, nonce2;
reg [31:0] nonce;
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_pipe66 p1 (
.clk(clk),
.state(midstate),
.state2(midstate),
.data({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash(hash)
);
sha256_pipe62 p2 (
.clk(clk),
.data({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash(hash2_w)
);
always @ (posedge clk)
begin
if ( reset )
begin
nonce <= 32'd129 + NONCE_OFFS;
nonce2 <= NONCE_OFFS + NONCE2_OFFS;
golden_nonce <= 32'd0;
end else begin
nonce <= nonce + NONCE_INCR;
nonce2 <= nonce2 + NONCE_INCR;
if ( hash2 == 32'ha41f32e7 )
begin
golden_nonce <= nonce2;
end
end
hash2 <= hash2_w;
end
endmodule
sha256_pipes.v
Code:
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: hash pipelines
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x}[1:0],{x}[31:2]} ^ {{x}[12:0],{x}[31:13]} ^ {{x}[21:0],{x}[31:22]} )
`define E1(x) ( {{x}[5:0],{x}[31:6]} ^ {{x}[10:0],{x}[31:11]} ^ {{x}[24:0],{x}[31:25]} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x}[6:4] ^ {x}[17:15], {{x}[3:0], {x}[31:7]} ^ {{x}[14:0],{x}[31:18]} ^ {x}[31:3] } )
`define S1(x) ( { {x}[16:7] ^ {x}[18:9], {{x}[6:0], {x}[31:17]} ^ {{x}[8:0],{x}[31:19]} ^ {x}[31:10] } )
module sha256_pipe_base ( clk, state, data, out );
parameter STAGES = 64;
input clk;
input [255:0] state;
input [511:0] data;
output [255:0] out;
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
genvar i;
generate
for (i = 0; i <= STAGES; i = i + 1) begin : S
wire [479:0] w_data;
wire [223:0] w_state;
wire [31:0] w_t1, w_data14;
if(i == 0)
sha256_stage0 #(
.K_NEXT(Ks[`IDX(63)]),
.STAGES(STAGES)
) I (
.clk(clk),
.i_data(data),
.i_state(state),
.o_data(w_data),
.o_state(w_state),
.o_t1(w_t1),
.o_data14(w_data14)
);
else
sha256_stage #(
.K_NEXT(Ks[`IDX((127-i) & 63)]),
.STAGES(STAGES)
) I (
.clk(clk),
.i_data(S[i-1].w_data),
.i_state(S[i-1].w_state),
.i_t1(S[i-1].w_t1),
.i_data14(S[i-1].w_data14),
.o_data(w_data),
.o_state(w_state),
.o_t1(w_t1),
.o_data14(w_data14)
);
end
endgenerate
reg [31:0] state7;
always @ (posedge clk)
begin
state7 <= S[STAGES-1].w_state[`IDX(6)];
end
assign out[255:224] = state7;
assign out[223:0] = S[STAGES].w_state;
endmodule
module sha256_pipe66 ( clk, state, state2, data, hash );
input clk;
input [255:0] state, state2;
input [511:0] data;
output reg [255:0] hash;
wire [255:0] out;
sha256_pipe_base #( .STAGES(64) ) P (
.clk(clk),
.state(state),
.data(data),
.out(out)
);
always @ (posedge clk)
begin
hash[`IDX(0)] <= state2[`IDX(0)] + out[`IDX(0)];
hash[`IDX(1)] <= state2[`IDX(1)] + out[`IDX(1)];
hash[`IDX(2)] <= state2[`IDX(2)] + out[`IDX(2)];
hash[`IDX(3)] <= state2[`IDX(3)] + out[`IDX(3)];
hash[`IDX(4)] <= state2[`IDX(4)] + out[`IDX(4)];
hash[`IDX(5)] <= state2[`IDX(5)] + out[`IDX(5)];
hash[`IDX(6)] <= state2[`IDX(6)] + out[`IDX(6)];
hash[`IDX(7)] <= state2[`IDX(7)] + out[`IDX(7)];
end
endmodule
module sha256_pipe62 ( clk, data, hash );
parameter state = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
input clk;
input [511:0] data;
output [31:0] hash;
wire [255:0] out;
sha256_pipe_base #( .STAGES(61) ) P (
.clk(clk),
.state(state),
.data(data),
.out(out)
);
assign hash = out[`IDX(4)];
endmodule
module sha256_pipe65 ( clk, state, data, hash );
input clk;
input [255:0] state;
input [511:0] data;
output [255:0] hash;
wire [255:0] out;
sha256_pipe_base #( .STAGES(64) ) P (
.clk(clk),
.state(state),
.data(data),
.out(out)
);
assign hash = out;
endmodule
module sha256_stage0 ( clk, i_data, i_state, o_data, o_state, o_t1, o_data14 );
parameter K_NEXT = 32'd0;
parameter STAGES = 64;
input clk;
input [511:0] i_data;
input [255:0] i_state;
output reg [479:0] o_data;
output reg [223:0] o_state;
output reg [31:0] o_t1, o_data14;
wire [31:0] s0;
always @ (posedge clk)
begin
o_data <= i_data[511:32];
o_state <= i_state[223:0];
o_t1 <= i_state[`IDX(7)] + i_data[`IDX(0)] + K_NEXT;
o_data14 <= `S0( i_data[`IDX(1)] ) + i_data[`IDX(0)];
end
endmodule
module sha256_stage ( clk, i_data, i_state, i_t1, i_data14, o_data, o_state, o_t1, o_data14 );
parameter K_NEXT = 32'd0;
parameter STAGES = 64;
input clk;
input [31:0] i_t1, i_data14;
input [479:0] i_data;
input [223:0] i_state;
output reg [479:0] o_data;
output reg [223:0] o_state;
output reg [31:0] o_t1, o_data14;
wire [31:0] t1 = `E1( i_state[`IDX(4)] ) + `CH( i_state[`IDX(4)], i_state[`IDX(5)], i_state[`IDX(6)] ) + i_t1;
wire [31:0] t2 = `E0( i_state[`IDX(0)] ) + `MAJ( i_state[`IDX(0)], i_state[`IDX(1)], i_state[`IDX(2)] );
wire [31:0] data14 = `S1( i_data[`IDX(13)] ) + i_data[`IDX(8)] + i_data14;
always @ (posedge clk)
begin
o_data[447:0] <= i_data[479:32];
o_data[`IDX(14)] <= data14;
o_state[`IDX(0)] <= t1 + t2;
o_state[`IDX(1)] <= i_state[`IDX(0)];
o_state[`IDX(2)] <= i_state[`IDX(1)];
o_state[`IDX(3)] <= i_state[`IDX(2)];
o_state[`IDX(4)] <= i_state[`IDX(3)] + t1;
o_state[`IDX(5)] <= i_state[`IDX(4)];
o_state[`IDX(6)] <= i_state[`IDX(5)];
o_t1 <= i_state[`IDX(6)] + i_data[`IDX(0)] + K_NEXT;
o_data14 <= `S0( i_data[`IDX(1)] ) + i_data[`IDX(0)];
end
endmodule
Please do not interpret this as me calling you a liar. You have obviously put a lot of work into your code and made numerous enhancements. I honestly wish you the best success with it. These numerous similarities just set off a lot of alarm bells for me and I hope you understand that. Help me to figure out why my coding style has leaked into your code and I will feel a lot better.
Thank you,
~fpgaminer
NOTE: GPG signed based on a plain-text copy of the text above. Just copy-paste the plain-text as it appears on the forum, so that BBCODE formatting is not included, to perform GPG signature verification.
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August 29, 2011, 06:12:17 PM
BTCMiner supports dynamic overclocking based on error measurement, i.e. the software scales the frequency such that a maximum rate of valid hashes is generated.
Aha - I remember you mentioning this on IRC. Cunning! Didn't realise that you were the person behind the ZTEX FPGA boards though... August 29, 2011, 04:57:36 PM
Things are getting interesting for FPGA mining.
Are you open to sell me a couple of boards with a nice discount, and get a deep review on it ?
I'm a 25 ghps experienced miner.
Are you open to sell me a couple of boards with a nice discount, and get a deep review on it ?
I'm a 25 ghps experienced miner.
August 29, 2011, 03:39:02 PM
ztex, just to be sure, the prices you mentioned in your first post are excl. VAT? And do you accept bitcoins for payment? 
Prices are without VAT. VAT has to by payed only by private customers from the EU.
EDIT - BTW, if customers from the EU order from outside the EU, they also have to pay import VAT.
FPGA boards (+ Base boards for the power supply) can be ordered at http://shop.ztex.de.
If you want to purchase more than 4 units or if you want a quotation in bitcoins (currently not supported in the shop due to the volatility) please use the contact Contact form.
August 29, 2011, 03:24:05 PM
ztex, just to be sure, the prices you mentioned in your first post are excl. VAT? And do you accept bitcoins for payment?
August 29, 2011, 02:50:35 PM
Those power and Mhash/s claims are a little outrageous. Be wary about this one until we have some better data
Maybe the power consumption #'s could be caused if ztex only measured the core power usage. The 6.8W number from our FPGA board was the total power usage of the board- including fan and regulator inefficiencies.
EDIT- and just after I post this, he changes the power #'s!! Fishy. From 2.8 to 5.9W on the LX150
Maybe the power consumption #'s could be caused if ztex only measured the core power usage. The 6.8W number from our FPGA board was the total power usage of the board- including fan and regulator inefficiencies.
EDIT- and just after I post this, he changes the power #'s!! Fishy. From 2.8 to 5.9W on the LX150
O.k. the initial power values where wrong because I used a faulty ampere meter as described above. It changed them from 3.6W (not 2.8W) to 5.9W on LX150 board. Sorry for that.
For those, who don't (want) to believe my results, here are some logs generated with the current version (http://www.ztex.de/btcminer/). These logs also show the
the overclocking feature in action.
This log was made with an USB-FPGA Module 1.15d started in single mode.
2011-08-29T18:13:34: ztex_ufm1_15d1-04A32DDEAF: New device: bitfile=ztex_ufm1_15d1 f_default=128,00MHz f_max=176,00MHz
2011-08-29T18:13:35: ztex_ufm1_15d1-04A32DDEAF: FPGA configuration time: 194 ms
2011-08-29T18:13:35: ztex_ufm1_15d1-04A32DDEAF: Set frequency to 128,00MHz
2011-08-29T18:13:50: ztex_ufm1_15d1-04A32DDEAF: f=128,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 0,0MH/s
2011-08-29T18:14:07: ztex_ufm1_15d1-04A32DDEAF: Error: connect timed out: Disabeling miner for 60s
2011-08-29T18:15:07: ztex_ufm1_15d1-04A32DDEAF: f=128,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 0,0MH/s
2011-08-29T18:15:22: ztex_ufm1_15d1-04A32DDEAF: f=128,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 0,0MH/s
2011-08-29T18:15:37: ztex_ufm1_15d1-04A32DDEAF: f=128,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 3 new nonces, measured hash rate 105,4MH/s
2011-08-29T18:15:52: ztex_ufm1_15d1-04A32DDEAF: f=128,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 1 new nonces, measured hash rate 125,1MH/s
2011-08-29T18:16:06: ztex_ufm1_15d1-04A32DDEAF: Set frequency to 136,00MHz
2011-08-29T18:16:07: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, submitted 1 new nonces, measured hash rate 140,8MH/s
2011-08-29T18:16:23: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 128,2MH/s
2011-08-29T18:16:38: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, submitted 4 new nonces, measured hash rate 211,4MH/s
2011-08-29T18:16:53: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 1 new nonces, measured hash rate 217,0MH/s
2011-08-29T18:17:08: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 201,7MH/s
2011-08-29T18:17:23: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 188,4MH/s
2011-08-29T18:17:23: ztex_ufm1_15d1-04A32DDEAF: Set frequency to 144,00MHz
2011-08-29T18:17:38: ztex_ufm1_15d1-04A32DDEAF: f=144,00MHz, errorRate=3,93%, maxErrorRate=1,97%, submitted 0 new nonces, measured hash rate 176,7MH/s
2011-08-29T18:17:46: ztex_ufm1_15d1-04A32DDEAF: Set frequency to 136,00MHz
2011-08-29T18:17:53: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, nextMaxErrorRate=6,11%, submitted 0 new nonces, measured hash rate 166,4MH/s
2011-08-29T18:18:20: ztex_ufm1_15d1-04A32DDEAF: Error: connect timed out: Disabeling miner for 60s
2011-08-29T18:19:20: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, nextMaxErrorRate=6,11%, submitted 0 new nonces, measured hash rate 124,4MH/s
2011-08-29T18:19:35: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, nextMaxErrorRate=6,11%, submitted 1 new nonces, measured hash rate 131,1MH/s
2011-08-29T18:19:50: ztex_ufm1_15d1-04A32DDEAF: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, nextMaxErrorRate=6,11%, submitted 1 new nonces, measured hash rate 137,3MH/s
Here is the same for USB-FPGA Module 1.15b
2011-08-29T19:05:36: ztex_ufm1_15b-04A32DCB9A: New device: bitfile=ztex_ufm1_15b f_default=128,00MHz f_max=176,00MHz
2011-08-29T19:05:37: ztex_ufm1_15b-04A32DCB9A: FPGA configuration time: 112 ms
2011-08-29T19:05:37: ztex_ufm1_15b-04A32DCB9A: Set frequency to 128,00MHz
2011-08-29T19:05:52: ztex_ufm1_15b-04A32DCB9A: f=128,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 0,0MH/s
2011-08-29T19:06:07: ztex_ufm1_15b-04A32DCB9A: f=128,00MHz, errorRate=0,00%, submitted 1 new nonces, measured hash rate 142,4MH/s
2011-08-29T19:06:22: ztex_ufm1_15b-04A32DCB9A: f=128,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 94,9MH/s
2011-08-29T19:06:37: ztex_ufm1_15b-04A32DCB9A: f=128,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 71,2MH/s
2011-08-29T19:06:51: ztex_ufm1_15b-04A32DCB9A: Set frequency to 136,00MHz
2011-08-29T19:06:52: ztex_ufm1_15b-04A32DCB9A: f=136,00MHz, submitted 1 new nonces, measured hash rate 113,8MH/s
2011-08-29T19:07:07: ztex_ufm1_15b-04A32DCB9A: f=136,00MHz, errorRate=0,00%, submitted 2 new nonces, measured hash rate 189,4MH/s
2011-08-29T19:07:22: ztex_ufm1_15b-04A32DCB9A: f=136,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 162,6MH/s
2011-08-29T19:07:38: ztex_ufm1_15b-04A32DCB9A: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 141,9MH/s
2011-08-29T19:07:53: ztex_ufm1_15b-04A32DCB9A: f=136,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 126,2MH/s
2011-08-29T19:08:07: ztex_ufm1_15b-04A32DCB9A: Set frequency to 144,00MHz
2011-08-29T19:08:08: ztex_ufm1_15b-04A32DCB9A: f=144,00MHz, submitted 0 new nonces, measured hash rate 113,6MH/s
2011-08-29T19:08:23: ztex_ufm1_15b-04A32DCB9A: f=144,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 103,3MH/s
2011-08-29T19:08:38: ztex_ufm1_15b-04A32DCB9A: f=144,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 94,7MH/s
2011-08-29T19:08:53: ztex_ufm1_15b-04A32DCB9A: f=144,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 87,4MH/s
2011-08-29T19:09:08: ztex_ufm1_15b-04A32DCB9A: f=144,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 81,2MH/s
2011-08-29T19:09:22: ztex_ufm1_15b-04A32DCB9A: Set frequency to 152,00MHz
2011-08-29T19:09:23: ztex_ufm1_15b-04A32DCB9A: f=152,00MHz, submitted 0 new nonces, measured hash rate 75,8MH/s
2011-08-29T19:09:38: ztex_ufm1_15b-04A32DCB9A: f=152,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 71,1MH/s
2011-08-29T19:09:53: ztex_ufm1_15b-04A32DCB9A: f=152,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 66,9MH/s
2011-08-29T19:10:09: ztex_ufm1_15b-04A32DCB9A: f=152,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 63,2MH/s
2011-08-29T19:10:24: ztex_ufm1_15b-04A32DCB9A: f=152,00MHz, errorRate=0,00%, maxErrorRate=0,00%, submitted 0 new nonces, measured hash rate 59,9MH/s
2011-08-29T19:10:36: ztex_ufm1_15b-04A32DCB9A: Set frequency to 160,00MHz
2011-08-29T19:10:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, submitted 1 new nonces, measured hash rate 71,1MH/s
2011-08-29T19:10:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,00%, submitted 0 new nonces, measured hash rate 67,8MH/s
2011-08-29T19:11:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,00%, submitted 1 new nonces, measured hash rate 77,6MH/s
2011-08-29T19:11:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,74%, maxErrorRate=0,96%, submitted 0 new nonces, measured hash rate 74,3MH/s
2011-08-29T19:11:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,47%, maxErrorRate=0,96%, submitted 0 new nonces, measured hash rate 71,2MH/s
2011-08-29T19:11:50: ztex_ufm1_15b-04A32DCB9A: Set frequency to 168,00MHz
2011-08-29T19:11:54: ztex_ufm1_15b-04A32DCB9A: f=168,00MHz, submitted 0 new nonces, measured hash rate 68,4MH/s
2011-08-29T19:11:57: ztex_ufm1_15b-04A32DCB9A: Set frequency to 160,00MHz
2011-08-29T19:12:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,27%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 1 new nonces, measured hash rate 76,7MH/s
2011-08-29T19:12:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,69%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 2 new nonces, measured hash rate 95,0MH/s
2011-08-29T19:12:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,49%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 1 new nonces, measured hash rate 101,8MH/s
2011-08-29T19:12:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,36%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 98,3MH/s
2011-08-29T19:13:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,26%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 95,0MH/s
2011-08-29T19:13:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,19%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 92,0MH/s
2011-08-29T19:13:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,14%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 89,1MH/s
2011-08-29T19:13:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,51%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 86,4MH/s
2011-08-29T19:14:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,38%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 83,9MH/s
2011-08-29T19:14:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,28%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 1 new nonces, measured hash rate 89,6MH/s
2011-08-29T19:14:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,21%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 87,2MH/s
2011-08-29T19:14:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,60%, maxErrorRate=0,96%, nextMaxErrorRate=5,86%, submitted 2 new nonces, measured hash rate 100,2MH/s
2011-08-29T19:15:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,93%, maxErrorRate=0,97%, nextMaxErrorRate=5,86%, submitted 0 new nonces, measured hash rate 97,6MH/s
2011-08-29T19:15:22: ztex_ufm1_15b-04A32DCB9A: Set frequency to 168,00MHz
2011-08-29T19:15:24: ztex_ufm1_15b-04A32DCB9A: f=168,00MHz, maxErrorRate=5,86%, submitted 1 new nonces, measured hash rate 102,4MH/s
2011-08-29T19:15:26: ztex_ufm1_15b-04A32DCB9A: Set frequency to 160,00MHz
2011-08-29T19:15:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=1,47%, maxErrorRate=1,54%, nextMaxErrorRate=6,63%, submitted 1 new nonces, measured hash rate 107,0MH/s
2011-08-29T19:15:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=1,57%, maxErrorRate=1,70%, nextMaxErrorRate=6,63%, submitted 1 new nonces, measured hash rate 111,4MH/s
2011-08-29T19:16:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=1,16%, maxErrorRate=1,70%, nextMaxErrorRate=6,63%, submitted 0 new nonces, measured hash rate 108,7MH/s
2011-08-29T19:16:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=1,32%, maxErrorRate=1,70%, nextMaxErrorRate=6,63%, submitted 0 new nonces, measured hash rate 106,2MH/s
2011-08-29T19:16:34: ztex_ufm1_15b-04A32DCB9A: Set frequency to 168,00MHz
2011-08-29T19:16:38: ztex_ufm1_15b-04A32DCB9A: Set frequency to 160,00MHz
2011-08-29T19:16:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=2,06%, maxErrorRate=2,06%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 103,8MH/s
2011-08-29T19:16:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=1,98%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 1 new nonces, measured hash rate 107,8MH/s
2011-08-29T19:17:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=1,48%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 105,5MH/s
2011-08-29T19:17:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=1,11%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 103,2MH/s
2011-08-29T19:17:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,83%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 101,1MH/s
2011-08-29T19:17:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,62%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 99,0MH/s
2011-08-29T19:18:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,46%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 1 new nonces, measured hash rate 102,8MH/s
2011-08-29T19:18:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,35%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 100,8MH/s
2011-08-29T19:18:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,26%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 98,8MH/s
2011-08-29T19:18:54: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,65%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 97,0MH/s
2011-08-29T19:19:09: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,89%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 1 new nonces, measured hash rate 100,5MH/s
2011-08-29T19:19:24: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,67%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 0 new nonces, measured hash rate 98,6MH/s
2011-08-29T19:19:39: ztex_ufm1_15b-04A32DCB9A: f=160,00MHz, errorRate=0,88%, maxErrorRate=2,41%, nextMaxErrorRate=7,43%, submitted 1 new nonces, measured hash rate 102,0MH/s
"measured hash rate" denotes the hash rate derived from the amount of submitted nonces. nextMaxErrorRate denotes the maximum error rate at the next frequnecy step (+8MHz). (errorRate is sometimes larger than maxErrorRate due to a different weight function)
One can see that the 1.15d board achieves 136 MHz. I tested several of these boards. Some achieve 136 MHz, some 144 MHz. At 144MHz there is usually a small error rate of a few percent. Only very few do the 144MHz without errors. Altogether the rate of valid hashes of all tested 1.15d board is between 135 MH/s and 144 MH/s.
I only tested one 1.15b board. But this one achieves 160MHz at an average error rate of about 1 percent, makes about 79 valid MH/s.
It is very unlikely that the difference of the "overclockability" comes from the difference of the design. (routability?) Nevertheless , I will try it out (two LX75 pipelines on one LX150). Probably the LX150 FPGA's are just slower.
Here are the par results from the from current implementation:
http://www.ztex.de/btcminer/ztex_ufm1_15d1.par
http://www.ztex.de/btcminer/ztex_ufm1_15b.par
The design goal was 160MHz in both cases. Of course, this is not achievable. The "Best case achievable" value from the par files is the clock period "guaranteed" by Xilinx. i.e. it is the minimum stable frequency.
newMeat1, you denote my hash rates as outrageous. Maybe you want to show us some results for your board (at least a par file).
August 29, 2011, 01:52:11 PM
While measuring power consumption is not trivial (Current compensated or voltage compensated) it should be clear to anyone being able to design a board. You learn this very early in electrical engineering.
This makes me wonder.
Protip: Practical power consumption should be measured at 115V/230V level before the power adapter since that is what you actually pay for.
It's not this big of a deal since the cos(phi) should be >0.99 anyway so eventual losses could be calculated but if you use a calibrated power meter it should still be the most accurate measurement.
This makes me wonder.
Protip: Practical power consumption should be measured at 115V/230V level before the power adapter since that is what you actually pay for.
It's not this big of a deal since the cos(phi) should be >0.99 anyway so eventual losses could be calculated but if you use a calibrated power meter it should still be the most accurate measurement.
August 29, 2011, 12:43:22 PM
I've a question about the USB-FPGA Module 1.15d. Version 1.15d isn't listed as supported by the SDK
The SDK description has to be updated. If you download the SDK, you can find a lot of examples for the 1.15d Board.
Quote
and the description of the v1.15d module says that the Xilinx ISE License is required. The free edition doesn't work with this fpga and the non-free license is freaking expensive . Is there a ready2go bitstream available?
2 x yes.. Is there a ready2go bitstream available?XC6LX150 FPGA's require a license or a 30 day evaluation license.
Bitstreams are included in the jar archive. If yo unpack it (using zip or so) you will find it in the FPGA subdirectory.
August 29, 2011, 12:19:28 PM
I've a question about the USB-FPGA Module 1.15d. Version 1.15d isn't listed as supported by the SDK and the description of the v1.15d module says that the Xilinx ISE License is required. The free edition doesn't work with this fpga and the non-free license is freaking expensive . Is there a ready2go bitstream available?
. Is there a ready2go bitstream available? August 29, 2011, 11:54:57 AM
Let's assume a best case scenario. $370 USD for 140 MH/s with $9 BTC/USD means it will take 1.5 years for this to pay for itself, assuming free electricity. If you have to pay for electricity, the time is even longer. Does this device come with a 2-year warranty?
To be honest, this scenario is still too optimistic
You have to take into account that the earnings / MHash will be reduced over the time and you also have to consider the risk of a crash. I wrote:
Quote
For amounts of 100 or larger a license production program can be offered which allow to build large clusters at competitive prices in comparison to GPUs.
In this case the costs would be reduced to 50% - 70% or even less, depending on the amounts you want to produce. August 29, 2011, 11:17:05 AM
Well, a 2-Ohm resistor would suck about half a watt of power. So that should make your # go up by 0.5W. But I can't think of any other reason why it would change your reading. We should be dealing with almost pure DC here.
I measured the voltage across the 2 Ohm resistor: 1.03 V and the voltage across the the Experimental Board (i.e. behind the resistor): 11.5V. This results in 11.5V * 1.03V / 2 Ohm = 5.92 W.
The ampere-meter, I used on Friday, seems to be absolutely inaccurate or damaged. Sorry for that wrong values.
August 29, 2011, 11:13:14 AM
Hardware:The FPGA Boards presented above is not optimal since it contains features which are not required for bitcoin mining. A cost optimized single board version with on-bord voltage regulators, but without DDR2 SDRAM, configuration booster CPLD, microSD and GPIO pins is scheduled for second half of September. The expected single unit price is 330 EUR (471 USD), expected 25 unit price is 260 EUR (370 USD).
Let's assume a best case scenario. $370 USD for 140 MH/s with $9 BTC/USD means it will take 1.5 years for this to pay for itself, assuming free electricity. If you have to pay for electricity, the time is even longer. Does this device come with a 2-year warranty? 
August 29, 2011, 11:00:42 AM
Well, a 2-Ohm resistor would suck about half a watt of power. So that should make your # go up by 0.5W. But I can't think of any other reason why it would change your reading. We should be dealing with almost pure DC here.
August 29, 2011, 10:48:36 AM
Can you ship internationally? This is awesome for us with high electricity bills.
yes, of course. The boards are shipped from Germany. Private customers from EU have to pay 19% German VAT.
August 29, 2011, 10:43:40 AM
I measured the power again, first with the old ampere meter (now I got 2.8W on the XC6SLX150 board), then with a 2 Ohm resister in series (voltage across the resistor). This seems to be more accurate: 3.6W on the LX75 Board and 5.9W on the LX150 board.
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