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Topic: BTCMiner - Open Source Bitcoin Miner for ZTEX FPGA Boards, 215 MH/s on LX150 - page 29. (Read 161727 times)

donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
Very awesome on the 190 achievment.  Is that primarily a chip limitation or is it possible to get any higher with good cooling and highly 'clean' power?  I.e., 88% PSUs, voltage regulation, and commercial grade ventilation?

It's a limitation of the bitstream (i.e the implemented design) and the FPGA.

'Clean power' does not help since core voltage quality is defined by the on board regulators, not he external voltage.

Standard cooling (with heatsink and fan) is more than sufficient.

The only thing that may help is to 'overvolt' the FPGA from (e.g. from 1.23V to 1.26V) by replacing one resistor.


rph
full member
Activity: 176
Merit: 100
Stupid question: doesn't this double the number of registers you need?

[Following up 1 month late..]

Using 2 cycles per stage does increase the number of registers, but nowhere near 2X. Multiple registers can be
packed very efficiently into SRL16s. So turning a 4 cycle delay into an 8 cycle delay has almost no marginal
area or power cost; they both use 1 SRL16.

-rph
hero member
Activity: 504
Merit: 500
A new BTCMiner release has been published at http://www.ztex.de/btcminer. With the new design typically about 190 MH/s can be achieved
on USB-FPGA Modules 1.15x (192 MHz at an error rate of less than 1%)

The data in the initial post has been updated.

Since the USB-FPGA Modules 1.15x are available now, I created a separate thread in the mining hardware section: https://bitcointalksearch.org/topic/ztex-usb-fpga-modules-115x-and-115y-215-and-860-mhs-fpga-boards-49180 This post also contains volume prices and estimated prices for license production programs.


  Very awesome on the 190 achievment.  Is that primarily a chip limitation or is it possible to get any higher with good cooling and highly 'clean' power?  I.e., 88% PSUs, voltage regulation, and commercial grade ventilation?
newbie
Activity: 45
Merit: 0
Is there a way to setup a way to setup a backup pool with BTCMiner?

No. I will add this to the todo list.

Well other than not having a backup pool option it is a great product with very reliable software.
donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
Is there a way to setup a way to setup a backup pool with BTCMiner?

No. I will add this to the todo list.
newbie
Activity: 45
Merit: 0
Is there a way to setup a way to setup a backup pool with BTCMiner?
donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
A new BTCMiner release has been published at http://www.ztex.de/btcminer. With the new design typically about 190 MH/s can be achieved
on USB-FPGA Modules 1.15x (192 MHz at an error rate of less than 1%)

The data in the initial post has been updated.

Since the USB-FPGA Modules 1.15x are available now, I created a separate thread in the mining hardware section: https://bitcointalksearch.org/topic/ztex-usb-fpga-modules-115x-and-115y-215-and-860-mhs-fpga-boards-49180 This post also contains volume prices and estimated prices for license production programs.
donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
The first 1.15x modules arrived yesterday.

Detailed product information (including schematics) and a new BTCMiner version (a few features still have to be added, e.g. hot-plug support in cluster mode) version will appear in the next days.

Those who don't want to wait can order the boards form the shop: http://shop.ztex.de/product_info.php?products_id=66. (prices for >4 units on request)
The boards run with the current BTCMiner version, but only at 135 MH/s. The new release will achieve about 190 MH/s.
donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
Quote
Stupid question: doesn't this double the number of registers you need?

In a two stage per sha256 round pipeline you also need approximately twice as much registers as in a one stage per round design.  The amount of registers per stage is approximately equal.
donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
Quote
How about the power consuming @187MH/s?

About 9W. Exact values follow.
donator
Activity: 980
Merit: 1004
felonious vagrancy, personified
Sharing is caring, so here's the business end of my VHDL. I'm planning to try
a few alternative options for the adders...

Code:
   two: if CYCLES = 2 generate
                -- second cycle
                o_data <= data;

Stupid question: doesn't this double the number of registers you need?

Your CYCLES=1 implementation appears to have one set of registers (o_data) whereas your CYCLES=2 implementation has two (o_data and data), though it's a bit difficult to be sure from just the segment you posted.

That's not necessarily a bad thing.  OTOH the map results you posted (elsewhere) show 50% register utilization, which doesn't seem like twice as many.  I must have missed something.
hero member
Activity: 592
Merit: 501
We will stand and fight.
Excellent news!

How does MHz translate to MH/s?

Is it roughly 1:1 or 2:1?

1:1, i.e. 187 MH/s

How about the power consuming @187MH/s?
donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
Excellent news!

How does MHz translate to MH/s?

Is it roughly 1:1 or 2:1?

1:1, i.e. 187 MH/s
c_k
donator
Activity: 242
Merit: 100
Excellent news!

How does MHz translate to MH/s?

Is it roughly 1:1 or 2:1?
donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
Just two updates:

Good news: I achieved 187 MHz non-overclocked. I'm still trying, but unless I find no faster design I will publish it with the next release. At this speed there is almost no overclocking possible.

There will be a further delay for the 1.15x boards: My assembler will try to deliver the boards at begin of next week.



donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
Very nice.  Even though not economical for me I may just have to buy one anyways.
If you are looking for a general purpose development board I recommend USB-FPGA Modules 1.15d or 1.15b (http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html) + Experimental Board 1.3. This combination contains RAM and a some other additional features and is also more flexible.
hero member
Activity: 592
Merit: 501
We will stand and fight.
donator
Activity: 1218
Merit: 1079
Gerald Davis
Very nice.  Even though not economical for me I may just have to buy one anyways.

donator
Activity: 367
Merit: 250
ZTEX FPGA Boards
The 1.15x sounds promising, how is it coming along?

I sent the parts to the assembler about 2.5 weeks ago. I expect the finished boards next week. (Currently assemblers in Germany are over allocated.)

The final USD price may be a little bit lower than the first estimate due to the weaker EUR (and due to the fact that I payed the parts when the EUR was stronger).

With updated software the boards will generate at least 160 MH/s.

Here are a few pictures of the prototype (with and w/o heat sinks):



c_k
donator
Activity: 242
Merit: 100
The 1.15x sounds promising, how is it coming along?
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