Took my most stable board (2.63 + 2.63U with twin-test), programmed to SPI and seems to work. After ~25 minutes I get:
cgminer version 2.5.0 - Started: [2012-07-26 19:20:12]
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(5s):1599.3 (avg):1495.8 Mh/s | Q:95 A:209 R:0 HW:0 E:220% U:7.5/m
TQ: 4 ST: 4 SS: 0 DW: 17 NB: 5 LW: 778 GF: 0 RF: 0
Connected to http://eu.ozco.in:8332 with LP as user zeta-mining.1
Block: 000008e19c79451adacd7c603a91be7f... Started: [19:40:07]
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[P]ool management [S]ettings [D]isplay options [Q]uit
ICA 0: | 367.8/372.6Mh/s | A:73 R:0 HW:0 U: 2.61/m
ICA 1: | 364.1/372.4Mh/s | A:75 R:0 HW:0 U: 2.68/m
ICA 2: | 373.9/372.8Mh/s | A:63 R:0 HW:0 U: 2.25/m
ICA 3: | 380.0/378.0Mh/s | A: 0 R:0 HW:0 U: 0.00/m
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As Glasswalker mentioned, one FPGA is idling (orange LED lit), but 7.5U is way better than 5.3U
For programming the DIP switches are to be set as Yohan was explaining in the post here, while for mining the mini-howto is almost complete: you need to switch all FPGA DIP switches (2-5) ON.
For those working with Linux, I am using the xc3sprog toolsuite natively, built from SVN with the patch I posted here and the following script (ran as sudo):
#!/bin/bash
BS=fpgaminer_top.bit
./xc3sprog -c cm1 -p0 -Ixc6lx150.bit $BS && \
./xc3sprog -c cm1 -p1 -Ixc6lx150.bit $BS && \
./xc3sprog -c cm1 -p2 -Ixc6lx150.bit $BS && \
./xc3sprog -c cm1 -p3 -Ixc6lx150.bit $BS && \
echo "Fertig" | zenity --info || { echo "Fatal error!" && echo "Fehler" | zenity --error; }
You'll need to build cgminer from source with the Baudrate set to 57.6k to mine.
Edit: copy-paste garbage fixed