Cairnsmore1 - Quad XC6SLX150 Board - page 77.

yohan

sr. member

Activity: 462

Merit: 251

Quote from: spiccioli on June 30, 2012, 05:45:06 AM

So I updated the controller FPGA on board serial n. 8 and it went withouth problems.

Then I started flashing twin_test.bit into my boards and I've found that outside of virtual box it takes a lot less to flash a FPGA.

Code:

user@t5570:~$ time sudo ./xc3sprog -c cm1 -p 3 -Ixc6lx150.bit twin_test.bit 
XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 674 $ OS: Linux
Free software: If you contribute nothing, expect nothing!
Feedback on success/failure/enhancement requests:
	http://sourceforge.net/mail/?group_id=170565 
Check Sourceforge for updates:
	http://sourceforge.net/projects/xc3sprog/develop

Using Libftdi, 
DNA is 0x390dc1e841c73bf1
JEDEC: 20 20 0x18 0x00
Found Numonyx Device, Device ID 0x2018
256 bytes/page, 65536 pages = 16777216 bytes total 
Verify: Success!

real	2m50.569s
user	0m4.340s
sys	0m10.517s

Less than 3 minutes per FPGA.

spiccioli.

Doing the direct programming of the FPGA is fast but won't stay when you power cycle. Loading ointo the SPI Flash takes longer but is there every time you power up the board.

spiccioli

legendary

Activity: 1378

Merit: 1003

nec sine labore

So I updated the controller FPGA on board serial n. 8 and it went withouth problems.

Then I started flashing twin_test.bit into my boards and I've found that outside of virtual box it takes a lot less to flash a FPGA.

Code:

user@t5570:~$ time sudo ./xc3sprog -c cm1 -p 3 -Ixc6lx150.bit twin_test.bit 
XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 674 $ OS: Linux
Free software: If you contribute nothing, expect nothing!
Feedback on success/failure/enhancement requests:
	http://sourceforge.net/mail/?group_id=170565 
Check Sourceforge for updates:
	http://sourceforge.net/projects/xc3sprog/develop

Using Libftdi, 
DNA is 0x390dc1e841c73bf1
JEDEC: 20 20 0x18 0x00
Found Numonyx Device, Device ID 0x2018
256 bytes/page, 65536 pages = 16777216 bytes total 
Verify: Success!

real	2m50.569s
user	0m4.340s
sys	0m10.517s

Less than 3 minutes per FPGA.

spiccioli.

yohan

sr. member

Activity: 462

Merit: 251

Looks like you guys have found at least one silly thing for me too look for today. When I get a chance I will ask about the -I thing and if we can in any way make it more consistant with the rest of the switches. If nothing else we can at least highlight that fact in the instructions.

spiccioli

legendary

Activity: 1378

Merit: 1003

nec sine labore

Quote from: daemonic on June 29, 2012, 09:55:21 PM

well done ebereon, ill sort another donation when im at my wallet machine

did you stick to the twin_test.bit or go with the 190M_V3.bit bitstream for the SPI

and proof for the -I is in the man page (http://xc3sprog.sourceforge.net/manpage.php) d'oh

Makes one wonder why every other option has a space but this one Sad

spiccioli

legendary

Activity: 1378

Merit: 1003

nec sine labore

Quote from: ebereon on June 29, 2012, 08:31:38 PM

If you want to flash both with one command, just do:

Code:

xc3sprog -c cm1 -p 0 -Ixc6lx150.bit twin_test.bit && xc3sprog -c cm1 -p 3 -Ixc6lx150.bit twin_test.bit

This will flash the first (0) and if it was ok, then the last one (3). And that takes ~16 minutes to finnish, just take a cup of coffee Wink

Thanks! Great finding that -I thing, I'm gonna flash mine as well.

spiccioli

ebereon

sr. member

Activity: 397

Merit: 500

Thanks guys for the donations! And happy flashing, don't forget the coffee! Wink

daemonic

newbie

Activity: 49

Merit: 0

Quote from: ebereon on June 29, 2012, 10:01:20 PM

I tested the 190M_V3.bit but it will not work, after power on the fpga with this bitstream have all led's on. Don't know why it is working in temp mode but not in SPI mode.

I stick to the twin_test.bit. Fingers crossed that it will work longer then my 14 hours max.

I just the found the same also, time to put twin_test.bit back on and leave it overnight now (3am) to see how it does Cheesy

ebereon

sr. member

Activity: 397

Merit: 500

Quote from: daemonic on June 29, 2012, 09:55:21 PM

well done ebereon, ill sort another donation when im at my wallet machine

did you stick to the twin_test.bit or go with the 190M_V3.bit bitstream for the SPI

and proof for the -I is in the man page (http://xc3sprog.sourceforge.net/manpage.php) d'oh

I tested the 190M_V3.bit but it will not work, after power on the fpga with this bitstream have all led's on. Don't know why it is working in temp mode but not in SPI mode.

I stick to the twin_test.bit. Fingers crossed that it will work longer then my 14 hours max.

testconpastas2

full member

Activity: 199

Merit: 100

please take my coffee invitation Wink

Thankyou again

daemonic

newbie

Activity: 49

Merit: 0

well done ebereon, ill sort another donation when im at my wallet machine

did you stick to the twin_test.bit or go with the 190M_V3.bit bitstream for the SPI

and proof for the -I is in the man page (http://xc3sprog.sourceforge.net/manpage.php) d'oh

ebereon

sr. member

Activity: 397

Merit: 500

Nice to see it's working for others too Cheesy

1KWGtSxo5b52Adk3Pvw14E3o9kp96JZJm2 Grin

gyverlb

hero member

Activity: 896

Merit: 1000

The -I no space trick is ... working!

This was the only thing that really prevented me to move the rig I use for the boards to the basement. No if there's a problem, in the worst case I can simply cut the power, wait a couple of seconds and restore the power and everything is back again mining.

Ok ebereon give us an address for donations.

testconpastas2

full member

Activity: 199

Merit: 100

thanks I'll do it. with this persistent way at least we'll be able of reseting in a fast way when any fpga become disabled.

ebereon

sr. member

Activity: 397

Merit: 500

Quote from: testconpastas2 on June 29, 2012, 08:26:20 PM

... here 2:24 am ...

Same here

ebereon

sr. member

Activity: 397

Merit: 500

If you want to flash both with one command, just do:

Code:

xc3sprog -c cm1 -p 0 -Ixc6lx150.bit twin_test.bit && xc3sprog -c cm1 -p 3 -Ixc6lx150.bit twin_test.bit

This will flash the first (0) and if it was ok, then the last one (3). And that takes ~16 minutes to finnish, just take a cup of coffee Wink

testconpastas2

full member

Activity: 199

Merit: 100

Ebereon you are great. here 2:24 am and just finished my first fpga of 12 boards.

all night awake!!!! thanks man Wink

ebereon

sr. member

Activity: 397

Merit: 500

Quote from: Keninishna on June 29, 2012, 08:22:15 PM

... I'm guessing this will load the SPI with the twin_flash.bit? So it won't need to be reprogrammed everytime I power off.

Yep! And it's working Cheesy

Keninishna

hero member

Activity: 556

Merit: 500

Quote from: ebereon on June 29, 2012, 06:36:07 PM

hmm, I can't let my fingers from it... Cheesy

I found the problem with flashing the bitstream to the SPI flash:

There is no blank betwen "-I" and the filename "xc6lx150.bit". I try now this, hope it works better when the unit is starting with the bitstream already loaded.

Edit:
When it's done it should look like this:

Wait until you see "Verify: Success". It takes 7:40 minutes per fpga!

What an odd bug... I'll have to give this a try on my board when I get home. I'm guessing this will load the SPI with the twin_flash.bit? So it won't need to be reprogrammed everytime I power off.

Doff

sr. member

Activity: 327

Merit: 250

Quote from: ebereon on June 29, 2012, 06:36:07 PM

hmm, I can't let my fingers from it... Cheesy

I found the problem with flashing the bitstream to the SPI flash:

There is no blank betwen "-I" and the filename "xc6lx150.bit". I try now this, hope it works better when the unit is starting with the bitstream already loaded.

Edit:
When it's done it should look like this:

Wait until you see "Verify: Success". It takes 7:40 minutes per fpga!

Nice, seems like an easy enough fix. Hope it works out for you ebereon.

ebereon

sr. member

Activity: 397

Merit: 500

hmm, I can't let my fingers from it... Cheesy

I found the problem with flashing the bitstream to the SPI flash:

There is no blank betwen "-I" and the filename "xc6lx150.bit". I try now this, hope it works better when the unit is starting with the bitstream already loaded.

Edit:
When it's done it should look like this:

Wait until you see "Verify: Success". It takes 7:40 minutes per fpga!

Topic: Cairnsmore1 - Quad XC6SLX150 Board - page 77. (Read 286370 times)