Topic: Cairnsmore1 - Quad XC6SLX150 Board - page 90. (Read 286370 times)
Okay thank you! I didn't know whether or not it was safe to change the DIP switches whilst the device is still switched on
@norulezapply, to program, i had;
SW6 all on
SW1 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
(as per progamming operation from virtual box, but ignoring the SW1 3 off)
then to use standard cgminer, i switched SW6 1 off;
SW6 1 off, 234 on
SW1 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
(as per normal operation)
(this is for twin_test.bit)
SW6 all on
SW1 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
(as per progamming operation from virtual box, but ignoring the SW1 3 off)
then to use standard cgminer, i switched SW6 1 off;
SW6 1 off, 234 on
SW1 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
(as per normal operation)
(this is for twin_test.bit)
You guys got it writing to the SPI flash too?
No,
just reprogrammed FPGA0 and FPGA3 without making this permanent.
spiccioli
Do you change the DIP settings back to "normal mode" after flashing?
Yes norulez,
as per twin_test.pdf page 1.
spiccioli
I managed to get it to work first time by having SW1/SW6 all on for the programming, then for my cgminer to work, i had to switch SW1 1 off again.
preliminary stats from cgminer API looks like 260MH/s from each PGA.
preliminary stats from cgminer API looks like 260MH/s from each PGA.
Ok
Mpbm shows a wrong speed as well, it's telling me that each FPGA is hashing at 378 MH/s, but my pool sees them both at around 280 MH/s
spiccioli
You guys got it writing to the SPI flash too?
No,
just reprogrammed FPGA0 and FPGA3 without making this permanent.
spiccioli
Do you change the DIP settings back to "normal mode" after flashing?
You guys got it writing to the SPI flash too?
I've done the first part successfully but when I'm trying to write to SPI flash I get "Unknown JDEC manufacturer: ff"
"ISF bitfile probably not loaded"
Not sure if I need to change the DIP switches to the ones in twin_test.bit now? Do I do the first part then change my DIP switches to match the "twin_test.bit" PDF file ones whilst it's still turned on or something?
I've done the first part successfully but when I'm trying to write to SPI flash I get "Unknown JDEC manufacturer: ff"
"ISF bitfile probably not loaded"
Not sure if I need to change the DIP switches to the ones in twin_test.bit now? Do I do the first part then change my DIP switches to match the "twin_test.bit" PDF file ones whilst it's still turned on or something?
No. I get the same error as you when trying the SPI flash.
You guys got it writing to the SPI flash too?
No,
just reprogrammed FPGA0 and FPGA3 without making this permanent.
spiccioli
I managed to get it to work first time by having SW1/SW6 all on for the programming, then for my cgminer to work, i had to switch SW6 1 off again.
preliminary stats from cgminer API looks like 380MH/s from each PGA??. (1 / 2.632e-9 = 379.93)
So to program, i had to have the same settings as atsoat;
details from cginer API;
so icarus-timing option would be 2.632=112 from what i learnt from kano
preliminary stats from cgminer API looks like 380MH/s from each PGA??. (1 / 2.632e-9 = 379.93)
So to program, i had to have the same settings as atsoat;
Code:
SW6 1 off, 234 on [ I actually had 1 on during programming, but not sure if this was necessary]
SW1 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
details from cginer API;
Code:
[read_count] => 112
[fullnonce] => 11.320125
[count] => 2
[Hs] => 0.000000002632127
so icarus-timing option would be 2.632=112 from what i learnt from kano
You guys got it writing to the SPI flash too?
I've done the first part successfully but when I'm trying to write to SPI flash I get "Unknown JDEC manufacturer: ff"
"ISF bitfile probably not loaded"
Not sure if I need to change the DIP switches to the ones in twin_test.bit now? Do I do the first part then change my DIP switches to match the "twin_test.bit" PDF file ones whilst it's still turned on or something?
I've done the first part successfully but when I'm trying to write to SPI flash I get "Unknown JDEC manufacturer: ff"
"ISF bitfile probably not loaded"
Not sure if I need to change the DIP switches to the ones in twin_test.bit now? Do I do the first part then change my DIP switches to match the "twin_test.bit" PDF file ones whilst it's still turned on or something?
daemonic,
keep trying, it took me a good 10 retries for -p 0 to complete, but in the end I was able to reprogram it.
-p 3 took three retries, before succeeding.
Right now I'm mining on ABC pool, using mpbm
spiccioli
keep trying, it took me a good 10 retries for -p 0 to complete, but in the end I was able to reprogram it.
-p 3 took three retries, before succeeding.
Right now I'm mining on ABC pool, using mpbm
spiccioli
I have an early board as well.
Try programming with:
SW1 1 off, 234 on [ I actually had 1 on during programming, but not sure if this was necessary]
SW6 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
And then run (without powering down inbetween) with the same config.
For the twin_test.bit only program 0 and 3.
Seems to have worked for me. I'm using the standard cgminer.
It seems to be faster and you now get a green light when it finds a nonce!
atsoat,
setting switches your way on my board (serial G2-0008) I can issue the programming command
Code:
xc3sprog -c cm1 -p0 twin_test.bit
but it fails with
Code:
Using Libftdi,
DNA is 0x19573723a1207bfe
Device failed to configure, INSTRUCTION_CAPTURE is 0x19
and on FPGA0 all leds remain lit, FPGA1-3 yellow led lit, spartan3 blinking red led.
spiccioli
I have an early board as well.
Try programming with:
SW1 1 off, 234 on [ I actually had 1 on during programming, but not sure if this was necessary]
SW6 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
And then run (without powering down inbetween) with the same config.
For the twin_test.bit only program 0 and 3.
Seems to have worked for me. I'm using the standard cgminer.
It seems to be faster and you now get a green light when it finds a nonce!
atsoat,
setting switches your way on my board (serial G2-0008) I can issue the programming command
Code:
xc3sprog -c cm1 -p0 twin_test.bit
but it fails with
Code:
Using Libftdi,
DNA is 0x19573723a1207bfe
Device failed to configure, INSTRUCTION_CAPTURE is 0x19
and on FPGA0 all leds remain lit, FPGA1-3 yellow led lit, spartan3 blinking red led.
spiccioli
I get as far as the programming stage when i need to set the dips and i get an error of
Code:
No JTAG Chain found
My Serial is 0018 and i seem to recall you mentioning the dip settings changed mid run at around number
Quote
Dip switches - One of things I have not quite got to as yet. One thing I was reminded about is that the functions on the Controller dip switches changed mid production ship so this might cause confusion when you are playing with them. The normal positions should be the same if I remember right but what they change differs. Hopefully that makes some sense. This change came in about board 26.
When i set 3 to off on SW6, i only get PGA 0 light up, all others are off?
My initial DIP settings also do not match the shipping test normal mode
SW1 was 1 off, 234 on
SW6 was all on
SW2 (PGA 0) was all on
SW3 (PGA 1) was 1 off, 234 on
SW4 (PGA 2) was 1 off, 234 on
SW5 (PGA 3) was all on
I have an early board as well.
Try programming with:
SW1 1 off, 234 on [ I actually had 1 on during programming, but not sure if this was necessary]
SW6 all on
SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on
And then run (without powering down inbetween) with the same config.
For the twin_test.bit only program 0 and 3.
Seems to have worked for me. I'm using the standard cgminer.
It seems to be faster and you now get a green light when it finds a nonce!
Are future boards shipping with the 2x190mhz firmware installed?
Yohan,
inside twin_test.pdf, page 2 and 3 are labelled
while page 1 is ok.
spiccioli
inside twin_test.pdf, page 2 and 3 are labelled
Code:
DIP Switch Settings for shipping_test.bit PROGRAMMING OPERATION
while page 1 is ok.
spiccioli
Dip switches are these same setting for both controller versions. There is some extra stuff to come to allow update of the controller using the same tools. Bitstream is already available if you have a programming cable and the tool can work that way as well to update the controller. If you are a power FPGA user and have it available ISE Impact can be used as well.
I'll have to take all the queries back to the engineer working on these bits so probably tomorrow before I have any response. Anything else anyone notices that needs fixing do let me know and I will try and get it all tidied up quickly. I wasn't expecting this to be a perfect process so it will probably be a bit buggy for a few days whilst we iron out the silly stuff. There is nothing better that the Microsoft way of debugging software. We are running a lot of this stuff in our line now so we might also suffer from being too familiar with the tools as well so we might have to add some things to the manuals.
I'll have to take all the queries back to the engineer working on these bits so probably tomorrow before I have any response. Anything else anyone notices that needs fixing do let me know and I will try and get it all tidied up quickly. I wasn't expecting this to be a perfect process so it will probably be a bit buggy for a few days whilst we iron out the silly stuff. There is nothing better that the Microsoft way of debugging software. We are running a lot of this stuff in our line now so we might also suffer from being too familiar with the tools as well so we might have to add some things to the manuals.
no success either.
No jtag chain found,
or
JEDEC: ff ff 0xff 0xff
unknown JEDEC manufacturer: ff
ISF Bitfile probably not loaded
one with the pdf settings to program, and the other with normal operation (the dip switch setting where the first jtag probing at the beginning of the manual is successful)
Board Serial 62-0016
I'll wait patiently
No jtag chain found,
or
JEDEC: ff ff 0xff 0xff
unknown JEDEC manufacturer: ff
ISF Bitfile probably not loaded
one with the pdf settings to program, and the other with normal operation (the dip switch setting where the first jtag probing at the beginning of the manual is successful)
Board Serial 62-0016
I'll wait patiently
Slight mistake in the guide so far;
I get as far as the programming stage when i need to set the dips and i get an error of
My Serial is 0018 and i seem to recall you mentioning the dip settings changed mid run at around number30 26?, so would i use the same settings as the pdf's show?
When i set 3 to off on SW1, i only get PGA 0 light up, all others are off?
My initial DIP settings also do not match the shipping test normal mode
SW6 was 1 off, 234 on
SW1 was all on
SW2 (PGA 0) was all on
SW3 (PGA 1) was 1 off, 234 on
SW4 (PGA 2) was 1 off, 234 on
SW5 (PGA 3) was all on
Quote
mount –t auto /dev/sdb /mnt
on page 10 should beQuote
mount –t auto /dev/sdb1 /mnt
I get as far as the programming stage when i need to set the dips and i get an error of
Code:
No JTAG Chain found
My Serial is 0018 and i seem to recall you mentioning the dip settings changed mid run at around number
Quote
Dip switches - One of things I have not quite got to as yet. One thing I was reminded about is that the functions on the Controller dip switches changed mid production ship so this might cause confusion when you are playing with them. The normal positions should be the same if I remember right but what they change differs. Hopefully that makes some sense. This change came in about board 26.
When i set 3 to off on SW1, i only get PGA 0 light up, all others are off?
My initial DIP settings also do not match the shipping test normal mode
SW6 was 1 off, 234 on
SW1 was all on
SW2 (PGA 0) was all on
SW3 (PGA 1) was 1 off, 234 on
SW4 (PGA 2) was 1 off, 234 on
SW5 (PGA 3) was all on
Programming utilities now available on http://www.enterpoint.co.uk/cairnsmore/cairnsmore1_support_materials.html "twin_test.bit" is bitstream to run 2 FPGAs at high performance level and will give the biggest mining returns currently.
D) The code is a bit strange, several things are... Wierd... in it. And it causes some problems, such as the boundry between clock domains between the comms code and the hashing cores, this causes in the default setup a clocking breakdown and the comms core fails, leaving the chip useless until it's restarted. There is also some over-sensitive settings on the hashing clock, which is why we had to underclock it to 50Mhz (over that the clock becomes unstable), which since the icarus code runs one hash per clock, that means 50MHash per chip. And a few other issues. Essentially it needs A LOT of hand holding to get it into a useful state at all.
There are seperate clock domains for the comms and hashing? Interesting. I hadn't really looked into it but was under the impression that the Icarus code was based on teknohog's clustering code and used a single clock domain for comms and hashing.
Jump to: