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Topic: Cairnsmore1 - Quad XC6SLX150 Board - page 92. (Read 286370 times)

hero member
Activity: 556
Merit: 500
June 19, 2012, 12:53:49 AM
We need firmware! what if the more advanced firmware reveals a bug in the hardware and no one can get all the fpgas running? Just food for thought.
That is the risk of buying pre-production hardware.

If you want safety, wait for the final/proven version before you buy.

Of course, the purchase cost is 50% higher at that point.

I do believe they are still selling it as a working piece of equipment that is all fpgas should work and would be covered under warranty. Now I don't think they have gaurenteed a hashrate yet so if it maxes out at like 300mhs thats another story :/
sr. member
Activity: 476
Merit: 250
June 18, 2012, 11:40:54 PM
We need firmware! what if the more advanced firmware reveals a bug in the hardware and no one can get all the fpgas running? Just food for thought.
That is the risk of buying pre-production hardware.

If you want safety, wait for the final/proven version before you buy.

Of course, the purchase cost is 50% higher at that point.
hero member
Activity: 556
Merit: 500
June 18, 2012, 11:36:31 PM
We need firmware! what if the more advanced firmware reveals a bug in the hardware and no one can get all the fpgas running? Just food for thought.
mem
hero member
Activity: 644
Merit: 501
Herp Derp PTY LTD
June 18, 2012, 10:17:44 PM
...
Questions
  • Any settings etc I should be wary of when getting these going ? (dont want to blow them 1st round)
...

I'm sure you can't blow it, i switched everything and it's hashing ~140Mh/s and cold as an refrigerator Grin

As Yohan stated some pages befor, the shipping switches should be:
SW1 all on
SW6 all on (57600 baud 100Mh/s, 1 off 115200 baud ~140Mh/s)

SW2 all on
SW3 134 on, 2 off
SW4 134 on, 2 off
SW5 all on



Thanks Cheesy


Yep, thanks heaps Glasswalker.

Guys sorry I have been a bit distant today and not done a few things I said I would do but thanks to *** I was run off my feet handling new orders and thanks to customers for all of those. I'm sure we will live up to everyones faith.

I have a complaint Yohan, you are being far to forth coming and honest about your product - please start ignoring and insulting your clients the way we FPGA bitcoiners  have become accustomed to. Wink

In all seriousness, you guys rock and its a pleasure to see a launch done right. (pre launch actually and that just makes it even more impressive).
newbie
Activity: 2
Merit: 0
June 18, 2012, 07:07:14 PM
The performance version with Ethernet support I don't have a timeline for as yet or a even full specification for as yet. It will come in it's own good time.
I'm very interested for such board. Either with Gigabit Ethernet or PCIe interface, but something with higher bandwidth and lower latency than the USB. At least one chip should be LX150T to achieve that. The chips on the board should be interconnected with each other with whatever means you find cost-efficient to maximize the cross-sectional bandwidth.

If you still haven't fully worked out the dual LX150 board then I urge you to consider connecting every free pin on the Spartans with each other, obeying the differential pair rules.

Thanks.

+1

PCIe preferable, but I'll take GigE Smiley
Maximising inter-FPGA bandwidth is also a great idea.
hero member
Activity: 481
Merit: 502
June 18, 2012, 05:48:19 PM
..
Shipping -Reached a new high today with the shipment heavier than the courier that came to collect it.
..

 Roll Eyes  Grin

Thanks for the update yohan.

Looking forward to getting my hands on the USB programming software!
sr. member
Activity: 462
Merit: 251
June 18, 2012, 05:34:21 PM
Guys sorry I have been a bit distant today and not done a few things I said I would do but thanks to *** I was run off my feet handling new orders and thanks to customers for all of those. I'm sure we will live up to everyones faith.

Dip switches - One of things I have not quite got to as yet. One thing I was reminded about is that the functions on the Controller dip switches changed mid production ship so this might cause confusion when you are playing with them. The normal positions should be the same if I remember right but what they change differs. Hopefully that makes some sense. This change came in about board 26. We are nearly ready to give out the programming software setup and that's already partially on our server albeit not linked in as yet. We are doing some final testing on virgin machines to check all is ok with that and putting together some instructions of how to use it all. Once that is in place everyone will be able to update their Cairnsmore1 Controllers to the latest standard. When this comes out we will be interested in any feedback on how we might make the process easier or better or indeed if you have any problems doing this.

Bitstreams - It is slow progress here and we are actually managing more time on our new original design that the Icarus rebuild. I am hoping that more time will be available as the week goes on and certainly next week. This isn't totally far from our own internal prediction for progress so I'm not worried by that and this more to reassure customers that it is moving albeit slowly. We are supported third party solutions as best we can so you are not just reliant on the Enterpoint team moving this forward. I expect we will reach a turning point fairly soon on what we are doing in bitstreams and then things will happen in a fairly fast and furious fashion.

Shipping -Reached a new high today with the shipment heavier than the courier that came to collect it. Our test, final assembly and packing lines showed a massive improvement today and the data looks very good. Numbers of boards that we struggled to handle last week were handled by half the staff with time to spare. That's fairly key to us taking a big step next on the primary assembly line where we go to running two P&P machines instead of one. It's very much a game of balancing the different processes and we have some to do there.

Clocking - We do have problem with 100MHz clock on one particular FPGA position however we think we have a firmware fix that will solve that. It's not been fully tested as yet. It's also possible to run between 25MHz and 50MHz and to multiple it up locally at the FPGA and that way is stable for all FPGAs and one definate way forward. Icarus builds already do this going 100MHz to 190MHz and we can do the same from 50MHz or 25MHz to 190MHz or whatever is appropriate for a given bitstream. This therefore should not be a problem to any of our customers beyond this initial phase.

hero member
Activity: 481
Merit: 502
June 18, 2012, 04:14:09 PM
It's just showing 0Mh/s, whereas the others all show 100Mh/s each.

The one pair is not starting propably, that's why i use mpbm atm. In mpbm i can restart only one COM and i do this until it starts up.

At the moment my unit is hashing @ ~175Mh/s checked on my pool 15 minutes average. One pair have over 60% invalids, that's the bitstream issue. Every time one of the fpga's on the bad pair is stopping (orange led) and don't get new work. It's waiting until it get's new job from the miner software.

I testing some settings atm to get it faster hashing with little succes. In mpbm i can change the job submit for each COM in seconds, standard is 60 and i changed that to 5 on the bad fpga pair.

I really don't know what i'm doing, but it's working so i'm happy Grin

Ah thanks, I didn't know that was what I had to do Smiley I'm running mpbm at the moment too, it's great IMO.

Same here with the invalids. Very very high but hashrate is still decent taking that into account.

Well kudos to you for fiddling around and pushing it to the limits Smiley
sr. member
Activity: 397
Merit: 500
June 18, 2012, 03:54:06 PM
It's just showing 0Mh/s, whereas the others all show 100Mh/s each.

The one pair is not starting propably, that's why i use mpbm atm. In mpbm i can restart only one COM and i do this until it starts up.

At the moment my unit is hashing @ ~175Mh/s checked on my pool 15 minutes average. One pair have over 60% invalids, that's the bitstream issue. Every time one of the fpga's on the bad pair is stopping (orange led) and don't get new work. It's waiting until it get's new job from the miner software.

I testing some settings atm to get it faster hashing with little succes. In mpbm i can change the job submit for each COM in seconds, standard is 60 and i changed that to 5 on the bad fpga pair.

I really don't know what i'm doing, but it's working so i'm happy Grin
hero member
Activity: 481
Merit: 502
June 18, 2012, 03:38:40 PM
With my approve settings and SW4 1 off, 234 on (this FPGA deactivated) i get ~143Mh/s on my pool. No more invalids  Still invalids ~30% Grin

Thanks for this info! I now have 100Mh/s from 3 of my 4 Cairnsmore1 COM ports (I have two Cairnsmore1's).

I'm not sure why only one of them isn't working though. Any ideas?

It's just showing 0Mh/s, whereas the others all show 100Mh/s each.
newbie
Activity: 17
Merit: 0
June 18, 2012, 03:15:57 PM
yohan, mail sent for ordering a unit of this promising fpga miner.
newbie
Activity: 49
Merit: 0
June 18, 2012, 02:40:41 PM
Glasswalker, thanks for the well thought/laid out explanation and thanks for everyone's efforts to get us this far Smiley
sr. member
Activity: 407
Merit: 250
June 18, 2012, 01:54:48 PM
I *thought* the Icarus bitstream could, was reported as able to, produce 400mh/s from these things while using only two of the four FPGAs. Is no one getting that?

It should, the problem with the default icarus bitstream is clock stability, it does it, but it seems to have clocking problems at the default rate. Anyone with the ability to reflash their boards should be able to reflash the default icarus bitstream to these, and try connecting, it should work with the first 2 chips only. at about 200MHash/s per chip. Provided they can get the clock stable. Ideally we need to modify the icarus bitstream to run at a lower clock source (say 50Mhz) and clock it up using an internal DCM to clock it up for hashing.

It should be noted that they initially designed the board with the hope that the icarus bitstream would run out of the box on this. The problem was there was a swap on 2 of the tx/rx pins from the first to second fpga in each "Icarus Chain". This means that only one of the chips hashes on the stock icarus bitstream.

Icarus is opensource, so several people (myself among them) have been working our butts off to do 2 things:
- Synthesize the icarus source code to a new "Cairnsmore" bitstream, which we've marginally succeeded at (resulting in the 50Mhz bitstream out now).
- Design a new bitstream from scratch that should easily beat the icarus bitstream.

The problem with re-synthesizing the icarus bitstream is that:
A) The source is distributed in a raw HDL format. Not including project files, compiler flags, pinouts, and other important bits needed to synthesize it. this requires a LOT of work to get the project ready to "compile" so to speak. Ultimately the open source project is "incomplete" in it's existing state.
B) Most of the time synthesis outright fails. P&R on this source is bad, and it has a hard time placing it all on the chip (I believe ngzhang did this by using a combination of Xilinx ISE and Synplify, without a "legit" license for these, which may be legal in his country but not here, and synplify is expensive)
C) Each run takes MANY hours, so you can only get a couple attempts in a single day (and yes I know you can fire up a cluster in EC2 and run PAR there, I've done that, on a cluster of about a dozen Double Extra Large instances in EC2, for a day, still didn't help matters so far, and yes it was expensive lol).
D) The code is a bit strange, several things are... Wierd... in it. And it causes some problems, such as the boundry between clock domains between the comms code and the hashing cores, this causes in the default setup a clocking breakdown and the comms core fails, leaving the chip useless until it's restarted. There is also some over-sensitive settings on the hashing clock, which is why we had to underclock it to 50Mhz (over that the clock becomes unstable), which since the icarus code runs one hash per clock, that means 50MHash per chip. And a few other issues. Essentially it needs A LOT of hand holding to get it into a useful state at all.

Since getting the basic build done (which was used to produce the 50Mhz bitstream), I've since given up on porting icarus over and moved back to building my own bitstream from scratch, designed for Cairnsmore. But that's also not a simple task. The reason I focused on Icarus initially was in the hope it would only take me a few days to hack together a usable 200Mhash bitstream. Unfortunately the level of effort is increasing drastically, and that time is better spent on the fresh bitstream.

At the same time the Enterpoint guys are still working to get the icarus bitstream "hacked" into a working state pulling at least close to 200MHash per chip.

Also the Tricone bitstream is an option as well which should be doable on these chips. Hopefully someone drives that forward as well, as it would be a good option for people to have (as it should pull close to 1GHash/s on these boards)

Lastly enterpoint has the skillset to make their own bitstream, but they have said that will be several months away. Right now their developers are all tied up, but their hardware team had cycles (which is why the boards could be made quickly). Once their developers are freed up they can likely bang out a nice bitstream for these boards.

The low performance is not indicitive of this board's actual performance, it's simply the fact that the icarus code is painful to work with, and due to one minor oversight (the swapped tx/rx, which is partially due to unclear source and lack of documentation on the icarus project), the icarus bitstream doesn't run out of the box on it. So the current options from a bitstream perspective are a bit lacking.

Overall this was all made clear in the beginning, Enterpoint has been awesome at keeping everyone in the loop during development and shipping. So hopefully either we get a hack working using the icarus based bitstream, or someone releases another bitstream for this board very soon that takes advantage of it's real potential.

I don't want to make any promises at all on my bitstream as it's too early to tell, and my time is limited (I have a day job to keep up with too lol).

So right now the way it stands, I managed to re-package and synthesize the icarus code into a usable bitstream, but it had issues. I sent that "complete" project and bitstream (along with ncd files and such) to Enterpoint, which they were able to tweak/adjust to get the current bitstreams in distribution. I'm not doing any further work on the icarus stuff, but hopefully they will make more progress.

I should have posted some of this info earlier, but I've been so busy the little time I have has been spent with blinders on working on the bitstream. So I had no idea this thread had progressed this far lol.

Hopefully this helps clarify some of the current bitstream situation.
member
Activity: 112
Merit: 10
June 18, 2012, 01:33:29 PM
Thanks Diablo !

kind regards
sr. member
Activity: 397
Merit: 500
June 18, 2012, 01:21:20 PM
Please can a mod split this offtopic stuff to another thread.
Or delete it.
Whichever is easier.

I split, stickied and locked it.

This is how BFL will do their penance.

https://bitcointalksearch.org/topic/the-thread-in-which-bfl-trolls-enterpoint-88363

Nice move, thank you!
legendary
Activity: 1162
Merit: 1000
DiabloMiner author
June 18, 2012, 01:17:23 PM
Please can a mod split this offtopic stuff to another thread.
Or delete it.
Whichever is easier.

I split, stickied and locked it.

This is how BFL will do their penance.

https://bitcointalksearch.org/topic/the-thread-in-which-bfl-trolls-enterpoint-88363
sr. member
Activity: 397
Merit: 500
June 18, 2012, 12:46:53 PM
With my original settings, the amber led is always on for the FPGA next to SW3/SW4

That means these FPGA's are idle (deactivated)

With your dip settings above, the amber led switches periodically between the FPGA next to SW4/SW5 and sometimes both on for a few seconds.

I know, it looks like the bitstream is buggy here, but i get ~140Mh/s with this settings instead of 100Mh/s
newbie
Activity: 49
Merit: 0
June 18, 2012, 12:44:15 PM
...
Questions
  • Any settings etc I should be wary of when getting these going ? (dont want to blow them 1st round)
...

I'm sure you can't blow it, i switched everything and it's hashing ~140Mh/s and cold as an refrigerator Grin

As Yohan stated some pages befor, the shipping switches should be:
SW1 all on
SW6 all on (57600 baud 100Mh/s, 1 off 115200 baud ~140Mh/s)

SW2 all on
SW3 134 on, 2 off
SW4 134 on, 2 off
SW5 all on
Mine came shipped as;
SW6 All on
SW1 1 off, 234 on

SW2 All on
SW3 1 off 234 on
SW4 1 off 234 on
SW5 All on

With your dip settings above, the amber led switches periodically between the FPGA next to SW4/SW5 and sometimes both on for a few seconds.
With my original settings, the amber led is always on for the FPGA next to SW3/SW4
sr. member
Activity: 397
Merit: 500
June 18, 2012, 12:17:44 PM
...
Questions
  • Any settings etc I should be wary of when getting these going ? (dont want to blow them 1st round)
...

I'm sure you can't blow it, i switched everything and it's hashing ~140Mh/s and cold as an refrigerator Grin

As Yohan stated some pages befor, the shipping switches should be:
SW1 all on
SW6 all on (57600 baud 100Mh/s, 1 off 115200 baud ~140Mh/s)

SW2 all on
SW3 134 on, 2 off
SW4 134 on, 2 off
SW5 all on

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