If Claymore cannot fix can use other miner software.
As I understand no other miner is better.
I don't see the link with drivers. I'm sure that AMD will fix the drivers if it can be improved as RX cards are losing popularity.
It seems linked to processor/memory architecture ?
Given how Claymore improved performance already from usual miners, If one miner software can get around the RX memory banking problem, I'm sure he will solve the problem, but I doubt any miner is better, and any driver can solve.
I've found some description of the algorithm. quickly reading it seems designed to be annoying, ie memory intensive, and memory is the problem behind RX slowdown (I did not find exactly the cause, except a vague reference to memory bank switch). If there is a solution it probably requires to neglect part of the 2.5 GB of data, maybe to focus on the neglected part later.
EDIT:
I have found the answer :
https://www.reddit.com/r/Amd/comments/6i1r5c/ethereum_hashrate_drop_for_radeon_rx400rx500_gpus/dj3ckli/
This particular slowdown is not directly related to memory speed, it's the result of translation lookaside buffer thrashing, and it's impact varies greatly from architecture to architecture and how the buffer was implemented. GPUs simply were not designed to make random accesses to a multi-GB contiguous chunk of data in VRAM.
Pitcairn (256bit) and Tahiti (384 bit) suffered greatly from this and have continually lost performance as the DAG grew, whereas Hawaii (512bit) and Tonga (256bit) were not significantly impacted and still get much the same hashrate they did last year.
In the fall of 2015 a tweaked 280x would get +27mh, today it would be lucky to see 15mh.
the 750Ti was hit super hard by this issue last year, with a steep plummet in hashrate down like 80%
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Translation lookaside buffer
A Translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location. It is a part of the chip’s memory-management unit (MMU). The TLB stores the recent translations of virtual memory to physical memory and can be called an address-translation cache. A TLB may reside between the CPU and the CPU cache, between CPU cache and the main memory or between the different levels of the multi-level cache. The majority of desktop, laptop, and server processors include one or more TLBs in the memory management hardware, and it is nearly always present in any processor that utilizes paged or segmented virtual memory.
the solution would be to try to localize some computation in space and time (eg: work on teh first half, then on the second half), but the algorithm is designed to be memory intensive...
as we say in french, Bon courage to Claymore...
this is not usual HPC, as the difficulty is not bad luck, but designed to be annoying.
